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Merge branch 'master' into qasm3
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renatomello committed Feb 14, 2024
2 parents 24314fc + 35d71fd commit d9dc16b
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Showing 5 changed files with 12 additions and 7 deletions.
7 changes: 3 additions & 4 deletions src/qibo/transpiler/blocks.py
Original file line number Diff line number Diff line change
Expand Up @@ -200,12 +200,11 @@ def block_decomposition(circuit: Circuit, fuse: bool = True):
remove_list = [first_block]
if len(initial_blocks[1:]) > 0:
for second_block in initial_blocks[1:]:
try:
if second_block.qubits == first_block.qubits:
first_block = first_block.fuse(second_block)
remove_list.append(second_block)
except BlockingError:
if not first_block.commute(second_block):
break
elif not first_block.commute(second_block):
break
blocks.append(first_block)
_remove_gates(initial_blocks, remove_list)

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8 changes: 6 additions & 2 deletions src/qibo/transpiler/router.py
Original file line number Diff line number Diff line change
Expand Up @@ -379,7 +379,9 @@ def __call__(self, circuit: Circuit, initial_layout: dict):
else:
self._find_new_mapping()

routed_circuit = self.circuit.routed_circuit(circuit_kwargs=circuit.init_kwargs)
circuit_kwargs = circuit.init_kwargs
circuit_kwargs["wire_names"] = list(initial_layout.keys())
routed_circuit = self.circuit.routed_circuit(circuit_kwargs=circuit_kwargs)
if self._final_measurements is not None:
routed_circuit = self._append_final_measurements(
routed_circuit=routed_circuit
Expand Down Expand Up @@ -658,7 +660,9 @@ def __call__(self, circuit: Circuit, initial_layout: dict):
else:
self._find_new_mapping()

routed_circuit = self.circuit.routed_circuit(circuit_kwargs=circuit.init_kwargs)
circuit_kwargs = circuit.init_kwargs
circuit_kwargs["wire_names"] = list(initial_layout.keys())
routed_circuit = self.circuit.routed_circuit(circuit_kwargs=circuit_kwargs)
if self._final_measurements is not None:
routed_circuit = self._append_final_measurements(
routed_circuit=routed_circuit
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2 changes: 1 addition & 1 deletion src/qibo/transpiler/unroller.py
Original file line number Diff line number Diff line change
Expand Up @@ -85,7 +85,7 @@ def __call__(self, circuit: Circuit):
Returns:
(:class:`qibo.models.circuit.Circuit`): equivalent circuit with native gates.
"""
translated_circuit = circuit.__class__(circuit.nqubits)
translated_circuit = Circuit(**circuit.init_kwargs)
for gate in circuit.queue:
translated_circuit.add(
translate_gate(
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1 change: 1 addition & 0 deletions tests/test_transpiler_pipeline.py
Original file line number Diff line number Diff line change
Expand Up @@ -237,6 +237,7 @@ def test_custom_passes_restict(gates, placer, routing):
final_layout=final_layout,
native_gates=NativeGates.default(),
)
assert transpiled_circ.wire_names == ["q1", "q2", "q3"]


def test_custom_passes_multiple_placer():
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1 change: 1 addition & 0 deletions tests/test_transpiler_router.py
Original file line number Diff line number Diff line change
Expand Up @@ -348,6 +348,7 @@ def test_restrict_qubits(router_algorithm):
)
assert_connectivity(restricted_connectivity, routed_circ)
assert_placement(routed_circ, final_layout, connectivity=restricted_connectivity)
assert routed_circ.wire_names == ["q0", "q2", "q3"]


def test_star_error_multi_qubit():
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