Add internal CI #1
GitHub Actions / verible-verilog-lint
failed
Aug 6, 2024 in 1s
reviewdog [verible-verilog-lint] report
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Findings (2)
test/synth/axi_memory_island_synth.sv|140 col 45| All generate block statements must have a label [Style: generate-statements] [generate-label]
test/synth/axi_memory_island_synth.sv|205 col 43| All generate block statements must have a label [Style: generate-statements] [generate-label]
Filtered Findings (0)
Annotations
Check warning on line 140 in test/synth/axi_memory_island_synth.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] test/synth/axi_memory_island_synth.sv#L140
All generate block statements must have a label [Style: generate-statements] [generate-label]
Raw output
message:"All generate block statements must have a label [Style: generate-statements] [generate-label]" location:{path:"./test/synth/axi_memory_island_synth.sv" range:{start:{line:140 column:45}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 205 in test/synth/axi_memory_island_synth.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] test/synth/axi_memory_island_synth.sv#L205
All generate block statements must have a label [Style: generate-statements] [generate-label]
Raw output
message:"All generate block statements must have a label [Style: generate-statements] [generate-label]" location:{path:"./test/synth/axi_memory_island_synth.sv" range:{start:{line:205 column:43}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
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