Add local DMA unit

.github/workflows/lint.yml

@@ -23,7 +23,8 @@ jobs:
           paths: |
             ./src
             ./test
-          exclude_paths:
+          exclude_paths: |
+            ./src/dma/memory_island_dma_generated.sv
           extra_args: "--rules=-interface-name-style --lint_fatal --parse_fatal"
           github_token: ${{ secrets.GITHUB_TOKEN }}
           reviewdog_reporter: github-check

Bender.lock

@@ -1,4 +1,11 @@
 packages:
+  apb:
+    revision: 77ddf073f194d44b9119949d2421be59789e69ae
+    version: 0.2.4
+    source:
+      Git: https://github.com/pulp-platform/apb.git
+    dependencies:
+    - common_cells
   axi:
     revision: 587355b77b8ce94dcd600efbd5d5bd118ff913a7
     version: 0.39.4
@@ -8,6 +15,13 @@ packages:
     - common_cells
     - common_verification
     - tech_cells_generic
+  axi_stream:
+    revision: 54891ff40455ca94a37641b9da4604647878cc07
+    version: 0.1.1
+    source:
+      Git: https://github.com/pulp-platform/axi_stream.git
+    dependencies:
+    - common_cells
   cluster_interconnect:
     revision: 7d0a4f8acae71a583a6713cab5554e60b9bb8d27
     version: 1.2.1
@@ -29,6 +43,36 @@ packages:
     source:
       Git: https://github.com/pulp-platform/common_verification.git
     dependencies: []
+  idma:
+    revision: c12caf59bb482fe44b27361f6924ad346b2d22fe
+    version: 0.6.3
+    source:
+      Git: https://github.com/pulp-platform/idma.git
+    dependencies:
+    - axi
+    - axi_stream
+    - common_cells
+    - common_verification
+    - obi
+    - register_interface
+  obi:
+    revision: c2141a653c755461ff44f61d12aeb5d99fc8e760
+    version: 0.1.3
+    source:
+      Git: https://github.com/pulp-platform/obi.git
+    dependencies:
+    - common_cells
+    - common_verification
+  register_interface:
+    revision: ae616e5a1ec2b41e72d200e5ab09c65e94aebd3d
+    version: 0.4.4
+    source:
+      Git: https://github.com/pulp-platform/register_interface.git
+    dependencies:
+    - apb
+    - axi
+    - common_cells
+    - common_verification
   tech_cells_generic:
     revision: 7968dd6e6180df2c644636bc6d2908a49f2190cf
     version: 0.2.13

Bender.yml

@@ -13,14 +13,19 @@ dependencies:
   cluster_interconnect: { git: "https://github.com/pulp-platform/cluster_interconnect.git", version: 1.2.1  }
   axi:                  { git: "https://github.com/pulp-platform/axi.git",                  version: 0.39.4 }
   common_verification:  { git: "https://github.com/pulp-platform/common_verification.git",  version: 0.2.0  }
+  idma:                 { git: "https://github.com/pulp-platform/idma.git",                 version: 0.6.2  }
+  register_interface:   { git: "https://github.com/pulp-platform/register_interface.git",   version: 0.4.4  }
+  obi:                  { git: "https://github.com/pulp-platform/obi.git",                  version: 0.1.3  }
 
 sources:
   # Level 0
+  - src/dma/memory_island_dma_generated.sv
   - src/mem_req_multicut.sv
   - src/mem_rsp_multicut.sv
   - src/stream_mem_to_banks_det.sv
   - src/varlat_inorder_interco.sv
   # Level 1
+  - src/dma/memory_island_dma.sv
   - src/memory_island_core.sv
   # Level 2
   - src/axi_memory_island_wrap.sv

Makefile

@@ -7,11 +7,31 @@
 MEMORY_ISLAND_ROOT := $(CURDIR)
 
 BENDER ?= bender -d $(MEMORY_ISLAND_ROOT)
+PYTHON ?= python
+
+IDMA_DIR := $(shell $(BENDER) path idma)
+
+-include $(IDMA_DIR)/idma.mk
+
+DMA_REG_HSJON := $(IDMA_RTL_DIR)/idma_reg32_3d.hjson
+DMA_REG_DEPS  := $(IDMA_RTL_DIR)/idma_reg32_3d_reg_pkg.sv
+DMA_REG_DEPS  += $(IDMA_RTL_DIR)/idma_reg32_3d_reg_top.sv
+DMA_REG_DEPS  += $(IDMA_RTL_DIR)/idma_reg32_3d_top.sv
+DMA_DEPS      := $(DMA_REG_DEPS)
+DMA_DEPS      += $(IDMA_RTL_DIR)/idma_transport_layer_rw_obi.sv
+DMA_DEPS      += $(IDMA_RTL_DIR)/idma_legalizer_rw_obi.sv
+DMA_DEPS      += $(IDMA_RTL_DIR)/idma_backend_rw_obi.sv
+
+src/dma/memory_island_dma_generated.sv: $(DMA_REG_HSJON) $(DMA_DEPS)
+	$(CAT) $(filter-out $<,$^) > $@
+
+.PHONY: dma-gen
+dma-gen: src/dma/memory_island_dma_generated.sv
 
 VSIM ?= vsim
 
 scripts/compile.tcl: Bender.yml Bender.lock
-	$(BENDER) script vsim -t test --vlog-arg="-svinputport=compat" > $@
+	$(BENDER) script vsim -t test -t rtl --vlog-arg="-svinputport=compat" > $@
 	echo "return 0" >> $@
 
 .PHONY: test-vsim

src/axi_memory_island_wrap.sv

@@ -56,6 +56,12 @@
   parameter int unsigned NarrowExtraBF        = 1,
   /// Words per memory bank. (Total number of banks is (WideWidth/NarrowWidth)*NumWideBanks)
   parameter int unsigned WordsPerBank         = 1024,
+  /// Use DMA
+  parameter bit          EnableDMA            = 1'b0,
+  /// Register types for DMA configuration
+  parameter type dma_reg_req_t                = logic,
+  parameter type dma_reg_rsp_t                = logic,
+
   // verilog_lint: waive explicit-parameter-storage-type
   parameter              MemorySimInit        = "none"
 ) (
@@ -66,14 +72,17 @@
   output axi_narrow_rsp_t [NumNarrowReq-1:0] axi_narrow_rsp_o,
 
   input  axi_wide_req_t   [  NumWideReq-1:0] axi_wide_req_i,
-  output axi_wide_rsp_t   [  NumWideReq-1:0] axi_wide_rsp_o
+  output axi_wide_rsp_t   [  NumWideReq-1:0] axi_wide_rsp_o,
+
+  input  dma_reg_req_t                       dma_reg_req_i,
+  output dma_reg_rsp_t                       dma_reg_rsp_o
 );
 
   localparam int unsigned NarrowStrbWidth = NarrowDataWidth/8;
   localparam int unsigned WideStrbWidth   = WideDataWidth/8;
 
   localparam int unsigned InternalNumNarrow = NumNarrowReq + $countones(NarrowRW);
-  localparam int unsigned InternalNumWide   = NumWideReq   + $countones(WideRW);
+  localparam int unsigned InternalNumWide   = NumWideReq   + $countones(WideRW) + (EnableDMA ? 2 : 0);
 
   localparam int unsigned NarrowMemRspLatency = SpillNarrowReqEntry +
                                                 SpillNarrowReqRouted +
@@ -231,13 +240,57 @@
     end
   end
 
+  if (EnableDMA) begin : gen_dma
+    memory_island_dma #(
+      .reg_req_t      ( dma_reg_req_t   ),
+      .reg_rsp_t      ( dma_reg_rsp_t   ),
+      .AddrWidth      ( AddrWidth       ),
+      .NarrowDataWidth( NarrowDataWidth ),
+      .WideDataWidth  ( WideDataWidth   ),
+      .MemoryLatency  ( SpillWideReqEntry + SpillWideReqRouted + SpillWideReqSplit +
+                        SpillWideRspSplit + SpillWideRspRouted + SpillWideRspEntry +
+                        SpillReqBank + SpillRspBank + 1 )
+    ) i_dma (
+      .clk_i,
+      .rst_ni,
+
+      .test_mode_i  ( '0 ),
+
+      .reg_req_i    ( dma_reg_req_i ),
+      .reg_rsp_o    ( dma_reg_rsp_o ),
+
+      .wide_req_o   ( wide_req    [InternalNumWide-:2] ),
+      .wide_gnt_i   ( wide_gnt    [InternalNumWide-:2] ),
+      .wide_addr_o  ( wide_addr   [InternalNumWide-:2] ),
+      .wide_we_o    ( wide_we     [InternalNumWide-:2] ),
+      .wide_wdata_o ( wide_wdata  [InternalNumWide-:2] ),
+      .wide_strb_o  ( wide_strb   [InternalNumWide-:2] ),
+      .wide_rvalid_i( wide_rvalid [InternalNumWide-:2] ),
+      .wide_rdata_i ( wide_rdata  [InternalNumWide-:2] )
+    );
+  end else begin : gen_dma_error_slv
+    if ($bits(dma_reg_rsp_t) > 1) begin : gen_actual_err_slv
+      reg_err_slv #(
+        .DW     (32),
+        .ERR_VAL('0),
+        .req_t  (dma_reg_req_t),
+        .rsp_t  (dma_reg_rsp_t)
+      ) i_reg_err (
+        .req_i(dma_reg_req_i),
+        .rsp_o(dma_reg_rsp_o)
+      );
+    end else begin : gen_tie_logic_0
+      assign dma_reg_rsp_o = '0;
+    end
+  end
+
 
   memory_island_core #(
     .AddrWidth            ( AddrWidth            ),
     .NarrowDataWidth      ( NarrowDataWidth      ),
     .WideDataWidth        ( WideDataWidth        ),
-    .NumNarrowReq         ( 2*NumNarrowReq       ),
-    .NumWideReq           ( 2*NumWideReq         ),
+    .NumNarrowReq         ( InternalNumNarrow    ),
+    .NumWideReq           ( InternalNumWide      ),
     .NumWideBanks         ( NumWideBanks         ),
     .NarrowExtraBF        ( NarrowExtraBF        ),
     .WordsPerBank         ( WordsPerBank         ),