Add initial linting CI

.github/verible.waiver

@@ -0,0 +1,6 @@
+# Copyright 2024 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+waive --rule=explicit-parameter-storage-type --location="src/memory_island_core.sv" --line=43
+waive --rule=explicit-parameter-storage-type --location="src/axi_memory_island_wrap.sv" --line=54

.github/workflows/lint.yml

@@ -0,0 +1,29 @@
+# Copyright 2024 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+
+# Author: Michael Rogenmoser <[email protected]>
+
+name: lint
+
+on:
+  push:
+    branches: [ main ]
+  pull_request:
+    branches: [ main ]
+  workflow_dispatch:
+
+jobs:
+  lint-verilog:
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v4
+      - uses: chipsalliance/verible-linter-action@main
+        with:
+          paths: |
+            ./src
+            ./test
+          exclude_paths:
+          extra_args: "--waiver_files .github/verible.waiver --rules=-interface-name-style --lint_fatal --parse_fatal"
+          github_token: ${{ secrets.GITHUB_TOKEN }}
+          reviewdog_reporter: github-check

src/axi_memory_island_wrap.sv

@@ -63,8 +63,8 @@ module axi_memory_island_wrap #(
   output axi_wide_rsp_t   [  NumWideReq-1:0] axi_wide_rsp_o
 );
 
-  localparam NarrowStrbWidth = NarrowDataWidth/8;
-  localparam WideStrbWidth   = WideDataWidth/8;
+  localparam int unsigned NarrowStrbWidth = NarrowDataWidth/8;
+  localparam int unsigned WideStrbWidth   = WideDataWidth/8;
 
   logic [2*NumNarrowReq-1:0]                      narrow_req;
   logic [2*NumNarrowReq-1:0]                      narrow_gnt;

src/mem_req_multicut.sv

@@ -35,14 +35,14 @@ module mem_req_multicut #(
 );
 
   localparam int unsigned AggDataWidth  = 1+StrbWidth+AddrWidth+DataWidth;
-  if (NumCuts == 0) begin
+  if (NumCuts == 0) begin : gen_passthrough
     assign req_o    = req_i;
     assign gnt_o    = gnt_i;
     assign addr_o   = addr_i;
     assign we_o     = we_i;
     assign wdata_o  = wdata_i;
     assign strb_o   = strb_i;
-  end else begin
+  end else begin : gen_cuts
     logic [NumCuts:0][AggDataWidth-1:0]  data_agg;
     logic [NumCuts:0] req, gnt;
 
@@ -53,7 +53,7 @@ module mem_req_multicut #(
     assign req_o        = req  [NumCuts];
     assign {we_o, strb_o, addr_o, wdata_o} = data_agg[NumCuts];
 
-    for (genvar i = 0; i < NumCuts; i++) begin
+    for (genvar i = 0; i < NumCuts; i++) begin : gen_cut
       spill_register #(
         .T     (logic[AggDataWidth-1:0]),
         .Bypass(1'b0)

src/mem_rsp_multicut.sv

@@ -24,11 +24,11 @@ module mem_rsp_multicut #(
   output logic [DataWidth-1:0] rdata_o
 );
 
-  if (NumCuts == 0) begin
+  if (NumCuts == 0) begin : gen_passthrough
     assign rvalid_o = rvalid_i;
     assign rready_o = rready_i;
     assign rdata_o  = rdata_i;
-  end else begin
+  end else begin : gen_cuts
     logic [NumCuts:0][DataWidth-1:0]  data_agg;
     logic [NumCuts:0] rvalid, rready;
 
@@ -39,7 +39,7 @@ module mem_rsp_multicut #(
     assign rvalid_o        = rvalid   [NumCuts];
     assign rdata_o         = data_agg [NumCuts];
 
-    for (genvar i = 0; i < NumCuts; i++) begin
+    for (genvar i = 0; i < NumCuts; i++) begin : gen_cut
       spill_register #(
         .T     (logic[DataWidth-1:0]),
         .Bypass(1'b0)

src/memory_island_core.sv

@@ -105,7 +105,13 @@ module memory_island_core #(
   localparam int unsigned NarrowAddrMemWidth = AddrTopBit-AddrNarrowWideBit;
   localparam int unsigned BankAddrMemWidth   = $clog2(WordsPerBank);
 
-  localparam int unsigned NarrowIntcBankLat = 1+SpillNarrowReqRouted+SpillNarrowRspRouted+SpillReqBank+SpillRspBank;
+  localparam int unsigned NarrowIntcBankLat = 1 +
+                                              SpillNarrowReqRouted +
+                                              SpillNarrowRspRouted +
+                                              SpillReqBank +
+                                              SpillRspBank;
+
+  localparam int unsigned PriorityWaitWidth = cf_math_pkg::idx_width(WidePriorityWait);
 
   logic [   NumNarrowReq-1:0]                                        narrow_req_entry_spill;
   logic [   NumNarrowReq-1:0]                                        narrow_gnt_entry_spill;
@@ -201,8 +207,9 @@ module memory_island_core #(
   logic [   NumWideBanks-1:0][NWDivisor-1:0][   NarrowStrbWidth-1:0] strb_bank_spill;
   logic [   NumWideBanks-1:0][NWDivisor-1:0][   NarrowDataWidth-1:0] rdata_bank_spill;
 
-  logic [   NumWideBanks-1:0][NWDivisor-1:0]                                               narrow_priority_req;
-  logic [   NumWideBanks-1:0][NWDivisor-1:0][cf_math_pkg::idx_width(WidePriorityWait)-1:0] wide_priority_d, wide_priority_q;
+  logic [   NumWideBanks-1:0][NWDivisor-1:0]                         narrow_priority_req;
+  logic [   NumWideBanks-1:0][NWDivisor-1:0][ PriorityWaitWidth-1:0] wide_priority_d,
+                                                                     wide_priority_q;
 
   for (genvar i = 0; i < NumNarrowReq; i++) begin : gen_narrow_entry_cuts
     mem_req_multicut #(
@@ -365,14 +372,19 @@ module memory_island_core #(
     // narrow gnt always set
     assign narrow_gnt_routed_spill = '1;
   end else begin : gen_narrow_gnt
-    for (genvar extraFactor = 0; extraFactor < NarrowExtraBF; extraFactor++) begin : gen_narrow_gnt_l1
-      for (genvar subBank = 0; subBank < NWDivisor; subBank++) begin : gen_narrow_gnt_l2
+    for (genvar extraFactor = 0;
+                extraFactor < NarrowExtraBF;
+                extraFactor++) begin : gen_narrow_gnt_l1
+      for (genvar subBank = 0;
+                  subBank < NWDivisor;
+                  subBank++) begin : gen_narrow_gnt_l2
         localparam int unsigned PseudoIdx = (extraFactor*NWDivisor) + subBank;
         always_comb begin
           narrow_gnt_routed_spill[(extraFactor*NWDivisor) + subBank] = '0;
           for (int wideBank = 0; wideBank < TotalBanks/WidePseudoBanks; wideBank++) begin
             if (narrow_addr_routed_spill [PseudoIdx][NarrowWideBankSelWidth-1:0] == wideBank) begin
-              narrow_gnt_routed_spill[PseudoIdx] = narrow_gnt_bank [(wideBank*NarrowExtraBF)+extraFactor][subBank];
+              narrow_gnt_routed_spill[PseudoIdx] =
+                narrow_gnt_bank [(wideBank*NarrowExtraBF)+extraFactor][subBank];
             end
           end
         end
@@ -381,14 +393,21 @@ module memory_island_core #(
   end
 
   // Route narrow requests to the correct bank, only requesting from the necessary banks
-  for (genvar wideBank = 0; wideBank < TotalBanks/WidePseudoBanks; wideBank++) begin : gen_narrow_routed_bank_l1
-    for (genvar extraFactor = 0; extraFactor < NarrowExtraBF; extraFactor++) begin : gen_narrow_routed_bank_l2
-      for (genvar subBank = 0; subBank < NWDivisor; subBank++) begin : gen_narrow_routed_bank_l3
+  for (genvar wideBank = 0;
+              wideBank < TotalBanks/WidePseudoBanks;
+              wideBank++) begin : gen_narrow_routed_bank_l1
+    for (genvar extraFactor = 0;
+                extraFactor < NarrowExtraBF;
+                extraFactor++) begin : gen_narrow_routed_bank_l2
+      for (genvar subBank = 0;
+                  subBank < NWDivisor;
+                  subBank++) begin : gen_narrow_routed_bank_l3
         localparam int unsigned WideBankIdx = (wideBank*NarrowExtraBF) + extraFactor;
         localparam int unsigned PseudoIdx   = (extraFactor*NWDivisor) + subBank;
         assign narrow_req_bank  [WideBankIdx][subBank] = narrow_req_routed_spill  [PseudoIdx] &
-                                                        (narrow_addr_routed_spill [PseudoIdx][NarrowWideBankSelWidth-1:0] == wideBank);
-        assign narrow_addr_bank [WideBankIdx][subBank] = narrow_addr_routed_spill [PseudoIdx][NarrowAddrMemWidth-1:NarrowWideBankSelWidth];
+          (narrow_addr_routed_spill [PseudoIdx][NarrowWideBankSelWidth-1:0] == wideBank);
+        assign narrow_addr_bank [WideBankIdx][subBank] =
+          narrow_addr_routed_spill [PseudoIdx][NarrowAddrMemWidth-1:NarrowWideBankSelWidth];
         assign narrow_we_bank   [WideBankIdx][subBank] = narrow_we_routed_spill   [PseudoIdx];
         assign narrow_wdata_bank[WideBankIdx][subBank] = narrow_wdata_routed_spill[PseudoIdx];
         assign narrow_strb_bank [WideBankIdx][subBank] = narrow_strb_routed_spill [PseudoIdx];
@@ -397,8 +416,12 @@ module memory_island_core #(
   end
 
   // Shift registers to properly select response data
-  for (genvar extraFactor = 0; extraFactor < NarrowExtraBF; extraFactor++) begin : gen_narrow_routed_bank_rdata_l1
-    for (genvar subBank = 0; subBank < NWDivisor; subBank++) begin : gen_narrow_routed_bank_rdata_l2
+  for (genvar extraFactor = 0;
+              extraFactor < NarrowExtraBF;
+              extraFactor++) begin : gen_narrow_routed_bank_rdata_l1
+    for (genvar subBank = 0;
+                subBank < NWDivisor;
+                subBank++) begin : gen_narrow_routed_bank_rdata_l2
       localparam int unsigned PseudoIdx = (extraFactor*NWDivisor) + subBank;
       logic [NarrowWideBankSelWidth-1:0] narrow_rdata_sel;
       shift_reg #(
@@ -410,7 +433,8 @@ module memory_island_core #(
         .d_i   ( narrow_addr_routed_spill [PseudoIdx][NarrowWideBankSelWidth-1:0] ),
         .d_o   ( narrow_rdata_sel                                                 )
       );
-      assign narrow_rdata_routed_spill[PseudoIdx] = narrow_rdata_bank[(narrow_rdata_sel*NarrowExtraBF) + extraFactor][subBank];
+      assign narrow_rdata_routed_spill[PseudoIdx] =
+        narrow_rdata_bank[(narrow_rdata_sel*NarrowExtraBF) + extraFactor][subBank];
     end
   end
 
@@ -594,13 +618,17 @@ module memory_island_core #(
       end
 
       // narrow/wide priority arbitration
-      assign req_bank             [i][j] =  narrow_req_bank    [i][j] | wide_req_bank_spill[i][j];
+      assign req_bank             [i][j] =  narrow_req_bank    [i][j] | wide_req_bank_spill  [i][j];
       assign narrow_gnt_bank      [i][j] =  narrow_priority_req[i][j];
       assign wide_gnt_bank_spill  [i][j] = ~narrow_priority_req[i][j];
-      assign we_bank              [i][j] =  narrow_priority_req[i][j] ? narrow_we_bank   [i][j] : wide_we_bank_spill   [i][j];
-      assign addr_bank            [i][j] =  narrow_priority_req[i][j] ? narrow_addr_bank [i][j] : wide_addr_bank_spill [i][j];
-      assign wdata_bank           [i][j] =  narrow_priority_req[i][j] ? narrow_wdata_bank[i][j] : wide_wdata_bank_spill[i][j];
-      assign strb_bank            [i][j] =  narrow_priority_req[i][j] ? narrow_strb_bank [i][j] : wide_strb_bank_spill [i][j];
+      assign we_bank              [i][j] =  narrow_priority_req[i][j] ? narrow_we_bank       [i][j]:
+                                                                        wide_we_bank_spill   [i][j];
+      assign addr_bank            [i][j] =  narrow_priority_req[i][j] ? narrow_addr_bank     [i][j]:
+                                                                        wide_addr_bank_spill [i][j];
+      assign wdata_bank           [i][j] =  narrow_priority_req[i][j] ? narrow_wdata_bank    [i][j]:
+                                                                        wide_wdata_bank_spill[i][j];
+      assign strb_bank            [i][j] =  narrow_priority_req[i][j] ? narrow_strb_bank     [i][j]:
+                                                                        wide_strb_bank_spill [i][j];
       assign narrow_rdata_bank    [i][j] =  rdata_bank         [i][j];
       assign wide_rdata_bank_spill[i][j] =  rdata_bank         [i][j];
 

src/varlat_inorder_interco.sv

@@ -7,48 +7,74 @@
 module varlat_inorder_interco #(
   ///////////////////////////
   // global parameters
-  parameter int unsigned                  NumIn           = 32,           // number of initiator ports (must be aligned with power of 2 for bfly and clos)
-  parameter int unsigned                  NumOut          = 64,           // number of TCDM banks (must be aligned with power of 2 for bfly and clos)
-  parameter int unsigned                  AddrWidth       = 32,           // address width on initiator side
-  parameter int unsigned                  DataWidth       = 32,           // word width of data
-  parameter int unsigned                  BeWidth         = DataWidth/8,  // width of corresponding byte enables
-  parameter int unsigned                  AddrMemWidth    = 12,           // number of address bits per TCDM bank
-  parameter bit                           WriteRespOn     = 1,            // defines whether the interconnect returns a write response
+  /// number of initiator ports (must be aligned with power of 2 for bfly and clos)
+  parameter int unsigned                  NumIn           = 32,
+  /// number of TCDM banks (must be aligned with power of 2 for bfly and clos)
+  parameter int unsigned                  NumOut          = 64,
+  /// address width on initiator side
+  parameter int unsigned                  AddrWidth       = 32,
+  /// word width of data
+  parameter int unsigned                  DataWidth       = 32,
+  /// width of corresponding byte enables
+  parameter int unsigned                  BeWidth         = DataWidth/8,
+  /// number of address bits per TCDM bank
+  parameter int unsigned                  AddrMemWidth    = 12,
+  /// defines whether the interconnect returns a write response
+  parameter bit                           WriteRespOn     = 1,
+  /// Number of outstanding requests supported
   parameter int unsigned                  NumOutstanding  = 1,
-  // determines the width of the byte offset in a memory word. normally this can be left at the default vaule,
-  // but sometimes it needs to be overridden (e.g. when meta-data is supplied to the memory via the wdata signal).
+  /// determines the width of the byte offset in a memory word. normally this can be left at the
+  /// default vaule, but sometimes it needs to be overridden (e.g. when meta-data is supplied to
+  /// the memory via the wdata signal).
   parameter int unsigned                  ByteOffWidth    = $clog2(DataWidth-1)-3,
 
-  // topology can be: LIC, BFLY2, BFLY4, CLOS
+  /// topology can be: LIC, BFLY2, BFLY4, CLOS
   parameter tcdm_interconnect_pkg::topo_e Topology        = tcdm_interconnect_pkg::LIC,
-  // number of parallel butterfly's to use, only relevant for BFLY topologies
+  /// number of parallel butterfly's to use, only relevant for BFLY topologies
   parameter int unsigned                  NumPar          = 1,
-  // this detemines which Clos config to use, only relevant for CLOS topologies
-  // 1: m=0.50*n, 2: m=1.00*n, 3: m=2.00*n
+  /// this detemines which Clos config to use, only relevant for CLOS topologies
+  /// 1: m=0.50*n, 2: m=1.00*n, 3: m=2.00*n
   parameter int unsigned                  ClosConfig      = 2
   ///////////////////////////
 ) (
   input  logic clk_i,
   input  logic rst_ni,
-  // master side
-  input  logic [ NumIn-1:0]                   req_i,     // request signal
-  input  logic [ NumIn-1:0][   AddrWidth-1:0] add_i,     // tcdm address
-  input  logic [ NumIn-1:0]                   we_i,      // 1: store, 0: load
-  input  logic [ NumIn-1:0][   DataWidth-1:0] wdata_i,   // write data
-  input  logic [ NumIn-1:0][     BeWidth-1:0] be_i,      // byte enable
-  output logic [ NumIn-1:0]                   gnt_o,     // grant (combinationally dependent on req_i and add_i
-  output logic [ NumIn-1:0]                   vld_o,     // response valid, also asserted if write responses ar
-  output logic [ NumIn-1:0][   DataWidth-1:0] rdata_o,   // data response (for load commands)
+  /// master side
+  /// request signal
+  input  logic [ NumIn-1:0]                   req_i,
+  /// tcdm address
+  input  logic [ NumIn-1:0][   AddrWidth-1:0] add_i,
+  /// 1: store, 0: load
+  input  logic [ NumIn-1:0]                   we_i,
+  /// write data
+  input  logic [ NumIn-1:0][   DataWidth-1:0] wdata_i,
+  /// byte enable
+  input  logic [ NumIn-1:0][     BeWidth-1:0] be_i,
+  /// grant (combinationally dependent on req_i and add_i
+  output logic [ NumIn-1:0]                   gnt_o,
+  /// response valid, also asserted if write responses ar
+  output logic [ NumIn-1:0]                   vld_o,
+  /// data response (for load commands)
+  output logic [ NumIn-1:0][   DataWidth-1:0] rdata_o,
   // slave side
-  output logic [NumOut-1:0]                   req_o,     // request out
-  input  logic [NumOut-1:0]                   gnt_i,     // grant input
-  output logic [NumOut-1:0][AddrMemWidth-1:0] add_o,     // address within bank
-  output logic [NumOut-1:0]                   we_o,      // write enable
-  output logic [NumOut-1:0][   DataWidth-1:0] wdata_o,   // write data
-  output logic [NumOut-1:0][     BeWidth-1:0] be_o,      // byte enable
+  /// request out
+  output logic [NumOut-1:0]                   req_o,
+  /// grant input
+  input  logic [NumOut-1:0]                   gnt_i,
+  /// address within bank
+  output logic [NumOut-1:0][AddrMemWidth-1:0] add_o,
+  /// write enable
+  output logic [NumOut-1:0]                   we_o,
+  /// write data
+  output logic [NumOut-1:0][   DataWidth-1:0] wdata_o,
+  /// byte enable
+  output logic [NumOut-1:0][     BeWidth-1:0] be_o,
+  /// response valid
   input  logic [NumOut-1:0]                   rvalid_i,
+  /// response ready
   output logic [NumOut-1:0]                   rready_o,
-  input  logic [NumOut-1:0][   DataWidth-1:0] rdata_i    // data response (for load commands)
+  /// data response (for load commands)
+  input  logic [NumOut-1:0][   DataWidth-1:0] rdata_i
 );
 
   localparam int unsigned NumOutLog2    = $clog2(NumOut);
@@ -63,7 +89,11 @@ module varlat_inorder_interco #(
     // extract bank index
     assign bank_sel[j] = add_i[j][ByteOffWidth+NumOutLog2-1:ByteOffWidth];
     // aggregate data to be routed to slaves
-    assign data_agg_in[j] = {we_i[j], be_i[j], add_i[j][ByteOffWidth+NumOutLog2+AddrMemWidth-1:ByteOffWidth+NumOutLog2], wdata_i[j]};
+    assign data_agg_in[j] = {we_i[j],
+                             be_i[j],
+                             add_i[j][ByteOffWidth+NumOutLog2+AddrMemWidth-1:
+                                      ByteOffWidth+NumOutLog2],
+                             wdata_i[j]};
   end
 
   // disaggregate data
@@ -106,7 +136,9 @@ module varlat_inorder_interco #(
 
     // Response path
     for (genvar i = 0; i < NumIn; i++) begin : gen_rsp
-      assign vld_o[i] = rvalid_i[bank_sel_rsp[i]] & rready_o[bank_sel_rsp[i]] & (ini_addr_rsp[bank_sel_rsp[i]] == i);
+      assign vld_o[i] = rvalid_i[bank_sel_rsp[i]] &
+                        rready_o[bank_sel_rsp[i]] &
+                        (ini_addr_rsp[bank_sel_rsp[i]] == i);
       assign rdata_o[i] = rdata_i[bank_sel_rsp[i]];
     end
     for (genvar i = 0; i < NumOut; i++) begin : gen_rready
@@ -160,7 +192,7 @@ module varlat_inorder_interco #(
         .pop_i     ( rvalid_i[i] & rready_o[i]             )
       );
     end
-  end else begin
+  end else begin : gen_fail
     $fatal(1, "unimplemented");
   end