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Modify configuration, simplify mem_to_banks logic
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micprog committed Aug 20, 2024
1 parent aef65a8 commit 5d88201
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Showing 3 changed files with 8 additions and 7 deletions.
4 changes: 2 additions & 2 deletions Bender.lock
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Expand Up @@ -16,8 +16,8 @@ packages:
dependencies:
- common_cells
common_cells:
revision: c27bce39ebb2e6bae52f60960814a2afca7bd4cb
version: 1.37.0
revision: c439813c28dda0d6b74e9b72539c546c9c15c5ae
version: null
source:
Git: https://github.com/pulp-platform/common_cells.git
dependencies:
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2 changes: 1 addition & 1 deletion Bender.yml
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Expand Up @@ -8,7 +8,7 @@ package:
- "Michael Rogenmoser <[email protected]>"

dependencies:
common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.37.0 }
common_cells: { git: "https://github.com/pulp-platform/common_cells.git", rev: c439813c28dda0d6b74e9b72539c546c9c15c5ae }
tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.13 }
cluster_interconnect: { git: "https://github.com/pulp-platform/cluster_interconnect.git", version: 1.2.1 }
axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.4 }
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9 changes: 5 additions & 4 deletions test/synth/axi_memory_island_synth.sv
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Expand Up @@ -10,13 +10,13 @@
module axi_memory_island_synth #(
localparam int unsigned AddrWidth = 32,
localparam int unsigned NarrowDataWidth = 32,
localparam int unsigned WideDataWidth = 512,
localparam int unsigned WideDataWidth = 256,

localparam int unsigned AxiIdWidth = 3,
localparam int unsigned AxiIdWidth = 2,

localparam int unsigned NumNarrowReq = 5,
localparam int unsigned NumNarrowReq = 6,
localparam int unsigned NumWideReq = 4,
localparam int unsigned WordsPerBank = 8192
localparam int unsigned WordsPerBank = 2048
) (
input logic clk_i,
input logic rst_ni,
Expand Down Expand Up @@ -280,6 +280,7 @@ module axi_memory_island_synth #(
.NumNarrowReq ( NumNarrowReq ),
.NumWideReq ( NumWideReq ),
.WordsPerBank ( WordsPerBank ),
.NumWideBanks (4),
.SpillNarrowReqEntry (0),
.SpillNarrowRspEntry (0),
.SpillNarrowReqRouted(0),
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