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Add parameter to support write- or read-only request ports
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@micprog
micprog committed Jul 25, 2024
1 parent 72b5a68 commit 44a6472
Showing 1 changed file with 139 additions and 71 deletions.
210 changes: 139 additions & 71 deletions src/axi_memory_island_wrap.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -26,6 +26,11 @@ module axi_memory_island_wrap #(
/// Number of Wide Ports
parameter int unsigned NumWideReq = 0,

/// Indicates corresponding narrow requestor supports read/write (0 for read-only/write-only)
parameter bit [NumNarrowReq-1:0] NarrowRW = '1,
/// Indicates corresponding narrow requestor supports read/write (0 for read-only/write-only)
parameter bit [NumWideReq-1:0] WideRW = '1,

/// Spill Narrow
parameter int unsigned SpillNarrowReqEntry = 0,
parameter int unsigned SpillNarrowRspEntry = 0,
Expand Down Expand Up @@ -63,83 +68,146 @@ module axi_memory_island_wrap #(
localparam NarrowStrbWidth = NarrowDataWidth/8;
localparam WideStrbWidth = WideDataWidth/8;

logic [2*NumNarrowReq-1:0] narrow_req;
logic [2*NumNarrowReq-1:0] narrow_gnt;
logic [2*NumNarrowReq-1:0][ AddrWidth-1:0] narrow_addr;
logic [2*NumNarrowReq-1:0][NarrowDataWidth-1:0] narrow_wdata;
logic [2*NumNarrowReq-1:0][NarrowStrbWidth-1:0] narrow_strb;
logic [2*NumNarrowReq-1:0] narrow_we;
logic [2*NumNarrowReq-1:0] narrow_rvalid;
logic [2*NumNarrowReq-1:0][NarrowDataWidth-1:0] narrow_rdata;

logic [ 2*NumWideReq-1:0] wide_req;
logic [ 2*NumWideReq-1:0] wide_gnt;
logic [ 2*NumWideReq-1:0][ AddrWidth-1:0] wide_addr;
logic [ 2*NumWideReq-1:0][ WideDataWidth-1:0] wide_wdata;
logic [ 2*NumWideReq-1:0][ WideStrbWidth-1:0] wide_strb;
logic [ 2*NumWideReq-1:0] wide_we;
logic [ 2*NumWideReq-1:0] wide_rvalid;
logic [ 2*NumWideReq-1:0][ WideDataWidth-1:0] wide_rdata;
localparam int unsigned InternalNumNarrow = NumNarrowReq + $countones(NarrowRW);
localparam int unsigned InternalNumWide = NumWideReq + $countones(WideRW);

logic [InternalNumNarrow-1:0] narrow_req;
logic [InternalNumNarrow-1:0] narrow_gnt;
logic [InternalNumNarrow-1:0][ AddrWidth-1:0] narrow_addr;
logic [InternalNumNarrow-1:0][NarrowDataWidth-1:0] narrow_wdata;
logic [InternalNumNarrow-1:0][NarrowStrbWidth-1:0] narrow_strb;
logic [InternalNumNarrow-1:0] narrow_we;
logic [InternalNumNarrow-1:0] narrow_rvalid;
logic [InternalNumNarrow-1:0][NarrowDataWidth-1:0] narrow_rdata;

logic [ InternalNumWide-1:0] wide_req;
logic [ InternalNumWide-1:0] wide_gnt;
logic [ InternalNumWide-1:0][ AddrWidth-1:0] wide_addr;
logic [ InternalNumWide-1:0][ WideDataWidth-1:0] wide_wdata;
logic [ InternalNumWide-1:0][ WideStrbWidth-1:0] wide_strb;
logic [ InternalNumWide-1:0] wide_we;
logic [ InternalNumWide-1:0] wide_rvalid;
logic [ InternalNumWide-1:0][ WideDataWidth-1:0] wide_rdata;


for (genvar i = 0; i < NumNarrowReq; i++) begin : gen_narrow_conv
axi_to_mem_split #(
.axi_req_t ( axi_narrow_req_t ),
.axi_resp_t ( axi_narrow_rsp_t ),
.AddrWidth ( AddrWidth ),
.AxiDataWidth ( NarrowDataWidth ),
.IdWidth ( AxiNarrowIdWidth ),
.MemDataWidth ( NarrowDataWidth ),
.BufDepth ( 2 ),
.HideStrb ( 1'b0 ),
.OutFifoDepth ( 1 )
) i_narrow_conv (
.clk_i,
.rst_ni,
.test_i ( '0 ),
.busy_o (),
.axi_req_i ( axi_narrow_req_i[ i ] ),
.axi_resp_o ( axi_narrow_rsp_o[ i ] ),
.mem_req_o ( narrow_req [2*i+:2] ),
.mem_gnt_i ( narrow_gnt [2*i+:2] ),
.mem_addr_o ( narrow_addr [2*i+:2] ),
.mem_wdata_o ( narrow_wdata [2*i+:2] ),
.mem_strb_o ( narrow_strb [2*i+:2] ),
.mem_atop_o (),
.mem_we_o ( narrow_we [2*i+:2] ),
.mem_rvalid_i ( narrow_rvalid [2*i+:2] ),
.mem_rdata_i ( narrow_rdata [2*i+:2] )
);
localparam id = i + $countones(NarrowRW[i:0]);
if (NarrowRW[i]) begin : gen_split_conv
axi_to_mem_split #(
.axi_req_t ( axi_narrow_req_t ),
.axi_resp_t ( axi_narrow_rsp_t ),
.AddrWidth ( AddrWidth ),
.AxiDataWidth ( NarrowDataWidth ),
.IdWidth ( AxiNarrowIdWidth ),
.MemDataWidth ( NarrowDataWidth ),
.BufDepth ( 2 ),
.HideStrb ( 1'b0 ),
.OutFifoDepth ( 1 )
) i_narrow_conv (
.clk_i,
.rst_ni,
.test_i ( '0 ),
.busy_o (),
.axi_req_i ( axi_narrow_req_i[i ] ),
.axi_resp_o ( axi_narrow_rsp_o[i ] ),
.mem_req_o ( narrow_req [id-:2] ),
.mem_gnt_i ( narrow_gnt [id-:2] ),
.mem_addr_o ( narrow_addr [id-:2] ),
.mem_wdata_o ( narrow_wdata [id-:2] ),
.mem_strb_o ( narrow_strb [id-:2] ),
.mem_atop_o (),
.mem_we_o ( narrow_we [id-:2] ),
.mem_rvalid_i ( narrow_rvalid [id-:2] ),
.mem_rdata_i ( narrow_rdata [id-:2] )
);
end else begin : gen_single_conv
axi_to_mem #(
.axi_req_t ( axi_narrow_req_t ),
.axi_resp_t ( axi_narrow_rsp_t ),
.AddrWidth ( AddrWidth ),
.AxiDataWidth ( NarrowDataWidth ),
.IdWidth ( AxiNarrowIdWidth ),
.NumBanks ( 1 ),
.BufDepth ( 2 ),
.HideStrb ( 1'b0 ),
.OutFifoDepth ( 1 )
) i_narrow_conv (
.clk_i,
.rst_ni,
.busy_o (),
.axi_req_i ( axi_narrow_req_i[i ] ),
.axi_resp_o ( axi_narrow_rsp_o[i ] ),
.mem_req_o ( narrow_req [id] ),
.mem_gnt_i ( narrow_gnt [id] ),
.mem_addr_o ( narrow_addr [id] ),
.mem_wdata_o ( narrow_wdata [id] ),
.mem_strb_o ( narrow_strb [id] ),
.mem_atop_o (),
.mem_we_o ( narrow_we [id] ),
.mem_rvalid_i ( narrow_rvalid [id] ),
.mem_rdata_i ( narrow_rdata [id] )
);
end
end

for (genvar i = 0; i < NumWideReq; i++) begin : gen_wide_conv
axi_to_mem_split #(
.axi_req_t ( axi_wide_req_t ),
.axi_resp_t ( axi_wide_rsp_t ),
.AddrWidth ( AddrWidth ),
.AxiDataWidth ( WideDataWidth ),
.IdWidth ( AxiWideIdWidth ),
.MemDataWidth ( WideDataWidth ),
.BufDepth ( 2 ),
.HideStrb ( 1'b0 ),
.OutFifoDepth ( 1 )
) i_wide_conv (
.clk_i,
.rst_ni,
.test_i ( '0 ),
.busy_o (),
.axi_req_i ( axi_wide_req_i[ i ] ),
.axi_resp_o ( axi_wide_rsp_o[ i ] ),
.mem_req_o ( wide_req [2*i+:2] ),
.mem_gnt_i ( wide_gnt [2*i+:2] ),
.mem_addr_o ( wide_addr [2*i+:2] ),
.mem_wdata_o ( wide_wdata [2*i+:2] ),
.mem_strb_o ( wide_strb [2*i+:2] ),
.mem_atop_o (),
.mem_we_o ( wide_we [2*i+:2] ),
.mem_rvalid_i ( wide_rvalid [2*i+:2] ),
.mem_rdata_i ( wide_rdata [2*i+:2] )
);
localparam id = i + $countones(WideRW[i:0]);
if (WideRW[i]) begin : gen_split_conv
axi_to_mem_split #(
.axi_req_t ( axi_wide_req_t ),
.axi_resp_t ( axi_wide_rsp_t ),
.AddrWidth ( AddrWidth ),
.AxiDataWidth ( WideDataWidth ),
.IdWidth ( AxiWideIdWidth ),
.MemDataWidth ( WideDataWidth ),
.BufDepth ( 2 ),
.HideStrb ( 1'b0 ),
.OutFifoDepth ( 1 )
) i_wide_conv (
.clk_i,
.rst_ni,
.test_i ( '0 ),
.busy_o (),
.axi_req_i ( axi_wide_req_i[i ] ),
.axi_resp_o ( axi_wide_rsp_o[i ] ),
.mem_req_o ( wide_req [id-:2] ),
.mem_gnt_i ( wide_gnt [id-:2] ),
.mem_addr_o ( wide_addr [id-:2] ),
.mem_wdata_o ( wide_wdata [id-:2] ),
.mem_strb_o ( wide_strb [id-:2] ),
.mem_atop_o (),
.mem_we_o ( wide_we [id-:2] ),
.mem_rvalid_i ( wide_rvalid [id-:2] ),
.mem_rdata_i ( wide_rdata [id-:2] )
);
end else begin : gen_single_conv
axi_to_mem #(
.axi_req_t ( axi_wide_req_t ),
.axi_resp_t ( axi_wide_rsp_t ),
.AddrWidth ( AddrWidth ),
.AxiDataWidth ( WideDataWidth ),
.IdWidth ( AxiWideIdWidth ),
.NumBanks ( 1 ),
.BufDepth ( 2 ),
.HideStrb ( 1'b0 ),
.OutFifoDepth ( 1 )
) i_wide_conv (
.clk_i,
.rst_ni,
.busy_o (),
.axi_req_i ( axi_wide_req_i[i ] ),
.axi_resp_o ( axi_wide_rsp_o[i ] ),
.mem_req_o ( wide_req [id] ),
.mem_gnt_i ( wide_gnt [id] ),
.mem_addr_o ( wide_addr [id] ),
.mem_wdata_o ( wide_wdata [id] ),
.mem_strb_o ( wide_strb [id] ),
.mem_atop_o (),
.mem_we_o ( wide_we [id] ),
.mem_rvalid_i ( wide_rvalid [id] ),
.mem_rdata_i ( wide_rdata [id] )
);
end
end


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