Release v0.3.0

CHANGELOG.md

@@ -5,7 +5,8 @@ All notable changes to this project will be documented in this file.
 The format is based on [Keep a Changelog](http://keepachangelog.com/), and this project adheres to
 [Semantic Versioning](http://semver.org).
 
-## Unreleased
+
+## 0.3.0 - 2022-03-11
 
 ### Added
 - Add testbench for `axi_riscv_atomics`
@@ -19,26 +20,31 @@ The format is based on [Keep a Changelog](http://keepachangelog.com/), and this
 - `axi_riscv_lrsc` now orders SWs and SCs in accordance with RVWMO (#4).
 - `axi_riscv_amos` use LR/SC to guarantee atomicity despite in-flight writes downstream.
 
+
 ## v0.2.2 - 2019-02-28
 
 ### Changed
 - Update `axi` dependency to v0.6.0 (from an intermediary commit).
 
+
 ## v0.2.1 - 2019-02-25
 
 ### Fixed
 - `axi_riscv_amos`: Fixed timing of R response (#10).
 
+
 ## v0.2.0 - 2019-02-21
 
 ### Changed
 - Made SystemVerilog interfaces optional.  Top-level modules now expose a flattened port list, and
   an optional wrapper provides SystemVerilog interfaces.  This improves compatibility with tools
   that have poor support for SystemVerilog interfaces.
 
+
 ## Fixed
 - `axi_riscv_amos`: Fixed burst, cache, lock, prot, qos, region, size, and user of ARs.
 
+
 ## v0.1.1 - 2019-02-20
 
 ### Fixed
@@ -56,6 +62,7 @@ The format is based on [Keep a Changelog](http://keepachangelog.com/), and this
 - Added simple standalone synthesis bench for `axi_riscv_atomics`.
 - Added simple standalone synthesis bench for `axi_riscv_lrsc`.
 
+
 ## v0.1.0 - 2019-02-19
 
 Initial public development release