adjust exception raise sequence in stc

parts/mem-access-insn.adoc

@@ -90,13 +90,13 @@ The STC instruction stores a capability to the memory.
 - `x[rs1].type` is `5` (sealed-return) and `x[rs1].async` is not `0` (synchronous).
 * `Insufficient capability permissions (27)`
 - `x[rs1].type` is `0` or `1`, and `2 \<=p x[rs1].perms` does not hold.
+* `Illegal operand value (29)`
+- `x[rs1].type` is `3` (uninitialised) and `imm` is not `0`.
 * `Capability out of bound (28)`
 - `x[rs1].type` is `0`, `1`, or `3`, and `x[rs1].cursor + imm` is
 not in the range `[x[rs1].base, x[rs1].end - CLENBYTES]`.
 - `x[rs1].type` is `5` or `6`, and `x[rs1].cursor + imm` is
 not in the range `[x[rs1].base + 3 * CLENBYTES, x[rs1].base + 33 * CLENBYTES - CLENBYTES]`.
-* `Illegal operand value (29)`
-- `x[rs1].type` is `3` (uninitialised) and `imm` is not `0`.
 * `Store/AMO address misaligned (6)`
 - `x[rs1].cursor + imm` is not aligned to `CLENBYTES` bytes.
 ****