Building 7020_hdmi

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Preparation

For the FPGA development with this project: See https://github.com/peteasa/parallella-fpga/tree/elink-redesign/AdiHDLLib/README.md for the version to install. At the time of writing this was vivado 2015.2.1

I have chosen to take a small set of library objects from those found at https://github.com/analogdevicesinc/hdl because building the whole library takes quite a bit of time with no real gain for this project. However I have taken the snapshot in a way that allows you to add from that library very easily if you have a project that requires more.

I have also added a top level Makefile and archived the first version of the 7020_hdmi project.. So to build the Analog Devices Inc libraries at parallella-fpga/AdiHDLLib and the two projects (7020_hdmi and 7010_hdmi). The method is quite easy.. just run make..

$ source /opt/xilinx/Vivado/2015.2/settings64.sh
$ cd parallella/parallella-fpga
$ make

I have proven both the 7020 and 7010 versions of this project but since I use the 7020 version of the parallella then the risk of finding problems with the 7010_hdmi project is greater than the risk of finding that the 7020_hdmi project is now broken.

Let me know how you get on...

Feedback is always welcome

FPGA development

I think that this link https://www.parallella.org/2015/03/23/new-parallella-elink-fpga-design-project-now-available-in-vivado/ provides and excellent introduction to getting started with the FPGA development. The project to open with Vivado is

$ vivado parallella/parallella-fpga/7020_hdmi/7020_hdmi.xpr

I will add a tutorial later about adding AXI DMA and the associated kernel drivers and device tree changes etc.

Generating the device tree

Once the FPGA changes you want have been implemented then you need to hand over the design to the software side. One key activity is to generate the device tree that describes the hardware to the software in a human / machine readable file. The process is well described at http://www.wiki.xilinx.com/Build+Device+Tree+Blob

1. In Vivado navigate to {Flow Navigator; IP Integrator; **Generate Block Design**} - leave the block design in the default location

   7020_hdmi/7020_hdmi.srcs/sources_1/bd/elink2_top/hw_handoff

2. In Vivado navigate to {File; Export; **Export Hardware**} - leave this in the default location:

   7020_hdmi/7020_hdmi.sdk

3. In Vivado navigate to {File; **Launch SDK**} - to start Eclipse with xilinx pluggins in the default locations

   7020_hdmi/7020_hdmi.sdk

4. in Eclipse {Xilinx Tools; Repositories; Add - **New**} and navigate to device-tree-xlnx.
5. in Eclipse {File; New; **Board Support Package**} - dont forget to select **device_tree** rather than **standalone** this will generate the device tree files in

   7020_hdmi/7020_hdmi.sdk/device_tree_bsp_0

The device tree created does not have everything but is a very good basis for creating the device tree to be used in the product. What I did was to read the device tree created with the additional hdmi IP and then modify by hand the device tree that I use in the Linux build. Dont forget that things like I²C and SPI busses may have external additional devices on the bus that are not represented in the Vivado tool so the device tree generated by Vivado is never going to be complete, but it gives you a good guide.

In an earlier version of the FPGA I noticed that the device tree did not show the correct interrupt line for PL-PS interrupts. This was not a bug in the device tree generation scripts but was due to the fact that I had forgotten to add the const block to tie unused interrupts to ground in the FPGA. So yes the device tree generation is good to do and review with care because it can provide a cross check that what you what is what you have generated in the bitstream!

The device-tree-xlnx source is at https://github.com/Xilinx/device-tree-xlnx.git and I have chosen to clone the commit that matches the version of Vivado that I use.

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