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    12 repositories

    • riscv-functional-sim

      Public
      Rust
      •0•0•0•0•Updated Dec 10, 2024Dec 10, 2024

    • baremetal-rust-riscv

      Public
      Rust
      •0•1•0•0•Updated Nov 29, 2024Nov 29, 2024

    • rocket-chip-publish

      Public
      CI to publish chipsalliance/rocket-chip SNAPSHOTs on Sonatype
      Python
      •0•1•0•0•Updated Nov 7, 2024Nov 7, 2024

    • power-analysis

      Public
      0•1•0•0•Updated Oct 31, 2024Oct 31, 2024

    • bus

      Public
      a bus
      Rust
      •0•0•0•0•Updated Oct 25, 2024Oct 25, 2024

    • egraph-synthesis-reading

      Public
      0•2•0•0•Updated Sep 30, 2024Sep 30, 2024

    • rtl-simulation-reading

      Public
      0•8•0•0•Updated Sep 17, 2024Sep 17, 2024

    • tidalsim

      Public
      Multi-level, sampled simulation using spike/uArch models/RTL for low latency, high fidelity, high throughput simulations
      Jupyter Notebook
      •0•5•0•2•Updated May 20, 2024May 20, 2024

    • chisel-recipes

      Public
      A Chisel DSL for imperative control flow machines.
      Scala
      •
      BSD 3-Clause "New" or "Revised" License
      •1•0•0•0•Updated Sep 15, 2023Sep 15, 2023

    • rtl2graph

      Public
      FIRRTL passes to transform a LoFIRRTL netlist to a graph for RTL embedding.
      Scala
      •0•3•0•0•Updated Sep 10, 2023Sep 10, 2023

    • .github

      Public
      0•0•0•0•Updated Sep 8, 2023Sep 8, 2023

    • simcommand

      Public
      SimCommand is a library for writing high-performance RTL testbenches with simulation threads in Scala using chiseltest.
      SystemVerilog
      •
      BSD 3-Clause "New" or "Revised" License
      •1•14•0•0•Updated Aug 30, 2023Aug 30, 2023