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Add FP8ALT (4,3) format support #131

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Add FP8ALT (4,3) format support #131

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3 changes: 2 additions & 1 deletion docs/README.md
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Original file line number Diff line number Diff line change
Expand Up @@ -134,10 +134,11 @@ Enumeration of type `logic [2:0]` holding the supported FP formats.
| `FP16` | IEEE binary16 | 16 bit | 5 | 10 |
| `FP8` | binary8 | 8 bit | 5 | 2 |
| `FP16ALT` | binary16alt | 16 bit | 8 | 7 |
| `FP8ALT` | binary8alt | 8 bit | 4 | 3 |

The following global parameters associated with FP formats are set in `fpnew_pkg`:
```SystemVerilog
localparam int unsigned NUM_FP_FORMATS = 5;
localparam int unsigned NUM_FP_FORMATS = 6;
localparam int unsigned FP_FORMAT_BITS = $clog2(NUM_FP_FORMATS);
```

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4 changes: 2 additions & 2 deletions src/fpnew_opgroup_multifmt_slice.sv
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Expand Up @@ -70,9 +70,9 @@ module fpnew_opgroup_multifmt_slice #(
if ((DivSqrtSel == fpnew_pkg::TH32) && !((FpFmtConfig[0] == 1) && (FpFmtConfig[1:NUM_FORMATS-1] == '0))) begin
$fatal(1, "T-Head-based DivSqrt unit supported only in FP32-only configurations. \
Set DivSqrtSel = THMULTI or DivSqrtSel = PULP to use a multi-format divider");
end else if ((DivSqrtSel == fpnew_pkg::THMULTI) && (FpFmtConfig[3] == 1'b1)) begin
end else if ((DivSqrtSel == fpnew_pkg::THMULTI) && (FpFmtConfig[3] == 1'b1 || FpFmtConfig[5] == 1'b1)) begin
$warning("The DivSqrt unit of C910 (instantiated by DivSqrtSel = THMULTI) does not support \
FP8. Please use the PULP DivSqrt unit when in need of div/sqrt operations on FP8.");
FP8, FP8alt. Please use the PULP DivSqrt unit when in need of div/sqrt operations on FP8, FP8alt.");
end
end

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25 changes: 14 additions & 11 deletions src/fpnew_pkg.sv
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Expand Up @@ -25,6 +25,7 @@ package fpnew_pkg;
// | FP16 | IEEE binary16 | 16 bit | 5 | 10
// | FP8 | binary8 | 8 bit | 5 | 2
// | FP16ALT | binary16alt | 16 bit | 8 | 7
// | FP8ALT | binary8alt | 8 bit | 4 | 3
// *NOTE:* Add new formats only at the end of the enumeration for backwards compatibilty!

// Encoding for a format
Expand All @@ -33,7 +34,7 @@ package fpnew_pkg;
int unsigned man_bits;
} fp_encoding_t;

localparam int unsigned NUM_FP_FORMATS = 5; // change me to add formats
localparam int unsigned NUM_FP_FORMATS = 6; // change me to add formats
localparam int unsigned FP_FORMAT_BITS = $clog2(NUM_FP_FORMATS);

// FP formats
Expand All @@ -42,7 +43,8 @@ package fpnew_pkg;
FP64 = 'd1,
FP16 = 'd2,
FP8 = 'd3,
FP16ALT = 'd4
FP16ALT = 'd4,
FP8ALT = 'd5
// add new formats here
} fp_format_e;

Expand All @@ -52,14 +54,15 @@ package fpnew_pkg;
'{11, 52}, // IEEE binary64 (double)
'{5, 10}, // IEEE binary16 (half)
'{5, 2}, // custom binary8
'{8, 7} // custom binary16alt
'{8, 7}, // custom binary16alt
'{4, 3} // custom binary8alt
// add new formats here
};

typedef logic [0:NUM_FP_FORMATS-1] fmt_logic_t; // Logic indexed by FP format (for masks)
typedef logic [0:NUM_FP_FORMATS-1][31:0] fmt_unsigned_t; // Unsigned indexed by FP format

localparam fmt_logic_t CPK_FORMATS = 5'b11000; // FP32 and FP64 can provide CPK only
localparam fmt_logic_t CPK_FORMATS = 6'b110000; // FP32 and FP64 can provide CPK only

// ---------
// INT TYPES
Expand Down Expand Up @@ -221,47 +224,47 @@ package fpnew_pkg;
Width: 64,
EnableVectors: 1'b0,
EnableNanBox: 1'b1,
FpFmtMask: 5'b11000,
FpFmtMask: 6'b110000,
IntFmtMask: 4'b0011
};

localparam fpu_features_t RV32D = '{
Width: 64,
EnableVectors: 1'b1,
EnableNanBox: 1'b1,
FpFmtMask: 5'b11000,
FpFmtMask: 6'b110000,
IntFmtMask: 4'b0010
};

localparam fpu_features_t RV32F = '{
Width: 32,
EnableVectors: 1'b0,
EnableNanBox: 1'b1,
FpFmtMask: 5'b10000,
FpFmtMask: 6'b100000,
IntFmtMask: 4'b0010
};

localparam fpu_features_t RV64D_Xsflt = '{
Width: 64,
EnableVectors: 1'b1,
EnableNanBox: 1'b1,
FpFmtMask: 5'b11111,
FpFmtMask: 6'b111111,
IntFmtMask: 4'b1111
};

localparam fpu_features_t RV32F_Xsflt = '{
Width: 32,
EnableVectors: 1'b1,
EnableNanBox: 1'b1,
FpFmtMask: 5'b10111,
FpFmtMask: 6'b101111,
IntFmtMask: 4'b1110
};

localparam fpu_features_t RV32F_Xf16alt_Xfvec = '{
Width: 32,
EnableVectors: 1'b1,
EnableNanBox: 1'b1,
FpFmtMask: 5'b10001,
FpFmtMask: 6'b100010,
IntFmtMask: 4'b0110
};

Expand Down Expand Up @@ -409,7 +412,7 @@ package fpnew_pkg;
// Returns the maximum number of lanes in the FPU according to width, format config and vectors
function automatic int unsigned num_divsqrt_lanes(int unsigned width, fmt_logic_t cfg, logic vec, divsqrt_unit_t DivSqrtSel);
automatic fmt_logic_t cfg_tmp;
cfg_tmp = (DivSqrtSel == THMULTI) ? cfg & 5'b11101 : cfg;
cfg_tmp = (DivSqrtSel == THMULTI) ? cfg & 6'b111010 : cfg;
return vec ? width / min_fp_width(cfg_tmp) : 1; // if no vectors, only one lane
endfunction

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