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luisacicolini committed Oct 1, 2024
1 parent 888925b commit 2311e78
Showing 1 changed file with 3 additions and 3 deletions.
6 changes: 3 additions & 3 deletions SSA/Experimental/Bits/Fast/FiniteStateMachine.lean
Original file line number Diff line number Diff line change
Expand Up @@ -453,12 +453,12 @@ def mapCircuit (c : Circuit (Fin n)) : FSM n where
case zero =>
simp [eval.next, next, BitVec.zero_width_append _, BitStream.head]
case succ m ih =>

simp [eval.next]
specialize ih xs.tails

simp at ih
rw [ih (xs.tails)]
-- rw [ih (xs.tails)]

sorry



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