v1.0.0

README.md

@@ -0,0 +1,7 @@
+# Core Template
+This is a template repository for a core which contains all of the core definition JSON files and FPGA starter code.
+
+## Legal
+Analogue’s Development program was created to further video game hardware preservation with FPGA technology. Analogue does not support or endorse the use of infringing content.
+
+Analogue Developers have access to Analogue Pocket I/O’s so Developers can utilize cartridge adapters or interface with other pieces of original or bespoke hardware to support legacy media.

audio.json

@@ -0,0 +1,5 @@
+{
+  "audio": {
+    "magic": "APF_VER_1" 
+  }
+}

core.json

@@ -0,0 +1,34 @@
+{
+    "core": {
+        "magic": "APF_VER_1",
+        "metadata": {
+            "platform_ids": [],
+            "shortname": "template",
+            "description": "Core template. Displays gray test screen.",
+            "author": "Developer",
+            "url": "https://github.com/open-fpga/core-template",
+            "version": "1.0",
+            "date_release": "2022-06-30"
+        },
+        "framework": {
+            "target_product": "Analogue Pocket",
+            "version_required": "1.1",
+            "sleep_supported": false,
+            "dock": {
+                "supported": true,
+                "analog_output": false
+            },
+            "hardware": {
+                "link_port": false,
+                "cartridge_adapter": -1
+            }
+        },
+        "cores": [
+            {
+                "name": "default",
+                "id": 0,
+                "filename": "bitstream.rbf_r"
+            }
+        ]
+    }
+}

data.json

@@ -0,0 +1,6 @@
+{
+    "data": {
+        "magic": "APF_VER_1",
+        "data_slots": []
+    }
+}

input.json

@@ -0,0 +1,6 @@
+{
+    "input": {
+        "magic": "APF_VER_1",
+        "controllers": []
+    }
+}

interact.json

@@ -0,0 +1,7 @@
+{
+    "interact": {
+        "magic": "APF_VER_1",
+        "variables": [],
+        "messages": []
+    }
+}

src/fpga/.gitignore

@@ -0,0 +1,28 @@
+*/db/
+*/incremental_db/
+*/simulation/
+*/greybox_tmp/
+incremental_db/
+db/
+PLLJ_PLLSPE_INFO.txt
+c5_pin_model_dump.txt
+cr_ie_info.json
+*.pin
+*.pof
+*.ptf.*
+*.qar
+*.qarlog
+*.qws
+*.rpt
+*.smsg
+*.sof
+*.sopc_builder
+*.summary
+*.txt
+*.bak
+*.cmp
+*.done
+*.xml
+*.sld
+*.cdf
+

src/fpga/ap_core.qpf

@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2019  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 18.1.1 Build 646 04/11/2019 SJ Lite Edition
+# Date created = 21:31:36  January 22, 2020
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "18.1"
+DATE = "21:31:36  January 22, 2020"
+
+# Revisions
+
+PROJECT_REVISION = "ap_core"