Prepare for release

NEWS

@@ -1,3 +1,29 @@
+1.5 2016-07-12 Olof Kindgren <[email protected]>
+======================================================
+* Improve plusargs handling
+* Fix core-info for verilator sections
+* Allow multiple top-level modules in Icarus
+* Fix VHDL and SystemVerilog support in ISIM
+* Add support for the GHDL simulator
+* Add support for Vivado Logicore cores
+* Add support for ISE CoreGen cores
+* Support IP-XACT 2009 and 2014 versions
+* Add icestorm backend
+* Allow settings default values for parameters
+* Add support for Altera qip files
+* Add CI testing with Travis and appveyor
+* Experimental Windows support
+* Allow Modelsim to run user TCL files
+* Parallelize verilator jobs to speed up compilation
+* + improved error handling, bug fixes and refactoring
+
+Contributors:
+Andrzej Radecki <[email protected]>
+Neil Turley <[email protected]>
+Olof Kindgren <[email protected]>
+Philipp Wagner <[email protected]>
+Stefan Wallentowitz <[email protected]>
+
 1.4 2016-01-29 Olof Kindgren <[email protected]>
 ======================================================
 * Allow setting top-level parameters in backends

setup.py

@@ -11,7 +11,7 @@ def read(fname):
               'fusesoc.ipyxact',
               'fusesoc.simulator',
               'fusesoc.provider'],
-    version = "1.4",
+    version = "1.5",
     author = "Olof Kindgren",
     author_email = "[email protected]",
     description = ("FuseSoC is a package manager and a set of build tools for HDL (Hardware Description Language) code."),