o1vm/riscv32: implement M type instruction Rem

[dannywillems]

No description provided.

[svv232]

it would be nice to comment the implementation from https://msyksphinz-self.github.io/riscv-isadoc/html/rvm.html

[codecov]

Codecov Report

Attention: Patch coverage is 0% with 11 lines in your changes missing coverage. Please review.

Project coverage is 71.94%. Comparing base (de7f623) to head (eaafc71).

Files with missing lines	Patch %	Lines
o1vm/src/interpreters/riscv32im/interpreter.rs	0.00%	11 Missing ⚠️

Additional details and impacted files

@@                               Coverage Diff                               @@
##           dw/o1vm/riscv32/remove-unused-divmod-signed    #2803      +/-   ##
===============================================================================
- Coverage                                        71.96%   71.94%   -0.03%     
===============================================================================
  Files                                              255      255              
  Lines                                            59992    60004      +12     
===============================================================================
- Hits                                             43173    43168       -5     
- Misses                                           16819    16836      +17     

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