o1vm/riscv32: implement mod_signed

[dannywillems]

It will be used to implement MInstruction::Rem in a follow-up PR.

[svv232]

Suggested change

	let x: u32 = (*x).try_into().unwrap();
	let y: u32 = (*y).try_into().unwrap();
	let res = ((x as i32) % (y as i32)) as u32;
	let res = res as u64;
	self.write_column(position, res);
	res
	let x: i32 = (*x).try_into().unwrap();
	let y: i32 = (*y).try_into().unwrap();
	let res = x % y;
	let res = res as u64;
	self.write_column(position, res);
	res

[codecov]

Codecov Report

Attention: Patch coverage is 0% with 21 lines in your changes missing coverage. Please review.

Project coverage is 71.93%. Comparing base (2340ce1) to head (8f304aa).

Files with missing lines	Patch %	Lines
o1vm/src/interpreters/riscv32im/witness.rs	0.00%	13 Missing ⚠️
o1vm/src/interpreters/riscv32im/constraints.rs	0.00%	8 Missing ⚠️

Additional details and impacted files

@@                           Coverage Diff                            @@
##           dw/o1vm/riscv32/implement-m-type-div    #2801      +/-   ##
========================================================================
- Coverage                                 71.95%   71.93%   -0.02%     
========================================================================
  Files                                       255      255              
  Lines                                     60000    60021      +21     
========================================================================
+ Hits                                      43173    43178       +5     
- Misses                                    16827    16843      +16     

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