o1vm/riscv32: implement M type instruction Mul

[dannywillems]

No description provided.

[svv232]

it would be nice to comment the implementation from https://msyksphinz-self.github.io/riscv-isadoc/html/rvm.html

[codecov]

Codecov Report

Attention: Patch coverage is 0% with 12 lines in your changes missing coverage. Please review.

Project coverage is 71.93%. Comparing base (f707007) to head (e0c1e89).
Report is 1 commits behind head on dw/riscv32-impl-mul-lo.

Files with missing lines	Patch %	Lines
o1vm/src/interpreters/riscv32im/interpreter.rs	0.00%	12 Missing ⚠️

Additional details and impacted files

@@                    Coverage Diff                     @@
##           dw/riscv32-impl-mul-lo    #2794      +/-   ##
==========================================================
- Coverage                   71.97%   71.93%   -0.04%     
==========================================================
  Files                         255      255              
  Lines                       59984    60019      +35     
==========================================================
+ Hits                        43172    43175       +3     
- Misses                      16812    16844      +32     

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