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feat(perf): Track last loads per block in mem2reg and remove them if possible #6088
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Changes to Brillig bytecode sizes
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Hmm this is surprising. I'm guessing that removing some of these loads is perhaps reducing the amount of trivial stores we can remove, but I'm not sure. |
The main difference between the SSA on master and this PR looks to be the
The repeat loads are removed in this PR, but those follow-up inc_rc instructions remain. I think this can be handled in a follow-up though so I am marking this PR ready for review again. |
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A couple cleanup notes, but otherwise LGTM
Looks like we are getting various regressions now after the RC correctness fix. Going to table this PR for now, and look at further optimizing RC instruction removals . |
Changes to number of Brillig opcodes executed
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Following some regressions from PR #6505 (#6505 (comment)) I decided to update this PR with master. It looks like we have some benefits from the optimizations aside for |
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still need to do a proper review but a couple of nits
Co-authored-by: Tom French <[email protected]>
…into mv/remove-last-loads-per-block
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LGTM. I'm still not 100% on the interactions with aliases here but I haven't been able to trick it with e.g. nested mutable references to create aliases, passing one of those to a function, mutating it, then loading again trying to get that load removed since only the alias was passed.
Description
Problem*
Resolves
Part of general effort to improve mem2reg.
Summary*
We sometimes have situations such as the following:
v2
does not have a known value, thus we do not remove the load. The mem2reg pass is acting as expected here. However, without a store or call to the reference betweenv11 = load v2
andv12 = load v2
we should be able to safely removev12 = load v2
and mapv12 -> v11
.This PR adds this logic as part of the initial mem2reg pass. We have a new
last_loads
map as part of aBlock
. This is currently cleared after analyzing block and is meant to only be per block. Unifying these last loads across blocks and the accurate predecessors can come in a follow-up. This is an initial proof of concept to show the optimizations validity.Given an instruction we act as following:
Load
Store
Call
I have also added two unit tests to
mem2reg.rs
Additional Context
Documentation*
Check one:
PR Checklist*
cargo fmt
on default settings.