Updated AXI st

Signed-off-by: Anderson Ignacio <[email protected]>
nasirkhansafi · Jul 3, 2022 · 4f89b2d · 4f89b2d
1 parent cdab9b7
commit 4f89b2d
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Showing 2 changed files with 9 additions and 5 deletions.
diff --git a/rtl/dma_axi_wrapper.sv b/rtl/dma_axi_wrapper.sv
@@ -61,7 +61,7 @@ module dma_axi_wrapper
     .i_rst_n                        (~rst),
     .i_awvalid                      (dma_csr_mosi_i.awvalid),
     .o_awready                      (dma_csr_miso_o.awready),
-    .i_awid                         ('0),
+    .i_awid                         (dma_csr_mosi_i.awid),
     .i_awaddr                       (dma_csr_mosi_i.awaddr),
     .i_awprot                       (dma_csr_mosi_i.awprot),
     .i_wvalid                       (dma_csr_mosi_i.wvalid),
@@ -70,16 +70,16 @@ module dma_axi_wrapper
     .i_wstrb                        (dma_csr_mosi_i.wstrb),
     .o_bvalid                       (dma_csr_miso_o.bvalid),
     .i_bready                       (dma_csr_mosi_i.bready),
-    .o_bid                          (),
+    .o_bid                          (dma_csr_miso_o.bid),
     .o_bresp                        (dma_csr_miso_o.bresp),
     .i_arvalid                      (dma_csr_mosi_i.arvalid),
     .o_arready                      (dma_csr_miso_o.arready),
-    .i_arid                         ('0),
+    .i_arid                         (dma_csr_mosi_i.arid),
     .i_araddr                       (dma_csr_mosi_i.araddr),
     .i_arprot                       (dma_csr_mosi_i.arprot),
     .o_rvalid                       (dma_csr_miso_o.rvalid),
     .i_rready                       (dma_csr_mosi_i.rready),
-    .o_rid                          (),
+    .o_rid                          (dma_csr_miso_o.rid),
     .o_rdata                        (dma_csr_miso_o.rdata),
     .o_rresp                        (dma_csr_miso_o.rresp),
     .o_dma_control_go               (dma_ctrl.go),

diff --git a/rtl/inc/axi_pkg.svh b/rtl/inc/axi_pkg.svh
@@ -39,7 +39,7 @@
   `endif
 
   `ifndef AXI_TXN_ID_WIDTH
-      `define AXI_TXN_ID_WIDTH    1
+      `define AXI_TXN_ID_WIDTH    8
   `endif
 
   typedef logic [`AXI_ADDR_WIDTH-1:0]      axi_addr_t;
@@ -157,18 +157,21 @@
     // Write Data channel
     logic           wready;
     // Write Response channel
+    axi_tid_t       bid;
     axi_error_t     bresp;
     logic           bvalid;
     // Read addr channel
     logic           arready;
     // Read data channel
+    axi_tid_t       rid;
     axi_data_t      rdata;
     axi_error_t     rresp;
     logic           rvalid;
   } s_axil_miso_t;
 
   typedef struct packed {
     // Write Address channel
+    axi_tid_t       awid;
     axi_addr_t      awaddr;
     axi_prot_t      awprot;
     logic           awvalid;
@@ -179,6 +182,7 @@
     // Write Response channel
     logic           bready;
     // Read Address channel
+    axi_tid_t       arid;
     axi_addr_t      araddr;
     axi_prot_t      arprot;
     logic           arvalid;