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CSRs tests working
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Signed-off-by: Anderson Ignacio <[email protected]>
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@aignacio
aignacio committed Jun 7, 2022
1 parent 66caea2 commit 32eec1a
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Showing 19 changed files with 217 additions and 324 deletions.
1 change: 1 addition & 0 deletions Dockerfile
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Expand Up @@ -7,6 +7,7 @@ RUN apt-get update && apt-get upgrade -y
RUN apt-get install git file make ruby -y
RUN gem install rggen
RUN gem install rggen-verilog
RUN gem update rggen-verilog

WORKDIR /
RUN git clone https://github.com/rggen/rggen-sv-rtl.git
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12 changes: 9 additions & 3 deletions Makefile
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@@ -1,14 +1,20 @@
# File : Makefile
# License : MIT license <Check LICENSE>
# Author : Anderson Ignacio da Silva (aignacio) <[email protected]>
# Date : 07.06.2022
# Last Modified Date: 07.06.2022

RUN_CMD := docker run --rm --name axi_dma \
-v $(abspath .):/axi_dma -w \
/axi_dma aignacio/axi_dma

.PHONY: run_test csr_dma.sv clean

all: csr_out
all: csr_out/csr_dma.v
$(RUN_CMD) tox

csr_out:
$(RUN_CMD) rggen --plugin rggen-verilog -c config.yml -o csr_out csr_dma.xlsx
csr_out/csr_dma.v:
$(RUN_CMD) rggen --plugin rggen-verilog -c config_csr.yml -o csr_out csr_dma.xlsx

clean:
@rm -rf run_dir csr_out
0 config.yml → config_csr.yml
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Binary file modified csr_dma.xlsx
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4 changes: 2 additions & 2 deletions csr_out/csr_dma.md
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Expand Up @@ -31,8 +31,8 @@

|name|bit_assignments|type|initial_value|reference|comment|
|:--|:--|:--|:--|:--|:--|
|done|[0]|ro|0x0||Asserted when DMA finishes to process all the descriptors|
|version|[16:1]|rof|0xcafe||DMA version|
|version|[15:0]|rof|0xcafe||DMA version|
|done|[16]|ro|0x0||Asserted when DMA finishes to process all the descriptors|
|error|[17]|ro|0x0|dma_error.error_trig|Error resume|

### <div id="csr_dma-dma_error"></div>dma_error
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38 changes: 19 additions & 19 deletions csr_out/csr_dma.sv
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Expand Up @@ -141,18 +141,17 @@ module csr_dma
.register_if (register_if[1]),
.bit_field_if (bit_field_if)
);
if (1) begin : g_done
localparam bit INITIAL_VALUE = 1'h0;
rggen_bit_field_if #(1) bit_field_sub_if();
`rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 1)
if (1) begin : g_version
localparam bit [15:0] INITIAL_VALUE = 16'hcafe;
rggen_bit_field_if #(16) bit_field_sub_if();
`rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 16)
rggen_bit_field #(
.WIDTH (1),
.WIDTH (16),
.STORAGE (0),
.EXTERNAL_READ_DATA (1),
.TRIGGER (0)
.EXTERNAL_READ_DATA (1)
) u_bit_field (
.i_clk (i_clk),
.i_rst_n (i_rst_n),
.i_clk ('0),
.i_rst_n ('0),
.bit_field_if (bit_field_sub_if),
.o_write_trigger (),
.o_read_trigger (),
Expand All @@ -161,23 +160,24 @@ module csr_dma
.i_hw_write_data ('0),
.i_hw_set ('0),
.i_hw_clear ('0),
.i_value (i_dma_status_done),
.i_value (INITIAL_VALUE),
.i_mask ('1),
.o_value (),
.o_value_unmasked ()
);
end
if (1) begin : g_version
localparam bit [15:0] INITIAL_VALUE = 16'hcafe;
rggen_bit_field_if #(16) bit_field_sub_if();
`rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 1, 16)
if (1) begin : g_done
localparam bit INITIAL_VALUE = 1'h0;
rggen_bit_field_if #(1) bit_field_sub_if();
`rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 16, 1)
rggen_bit_field #(
.WIDTH (16),
.WIDTH (1),
.STORAGE (0),
.EXTERNAL_READ_DATA (1)
.EXTERNAL_READ_DATA (1),
.TRIGGER (0)
) u_bit_field (
.i_clk ('0),
.i_rst_n ('0),
.i_clk (i_clk),
.i_rst_n (i_rst_n),
.bit_field_if (bit_field_sub_if),
.o_write_trigger (),
.o_read_trigger (),
Expand All @@ -186,7 +186,7 @@ module csr_dma
.i_hw_write_data ('0),
.i_hw_set ('0),
.i_hw_clear ('0),
.i_value (INITIAL_VALUE),
.i_value (i_dma_status_done),
.i_mask ('1),
.o_value (),
.o_value_unmasked ()
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70 changes: 35 additions & 35 deletions csr_out/csr_dma.v
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Expand Up @@ -112,14 +112,14 @@ module csr_dma #(
wire [31:0] w_bit_field_write_data;
wire [31:0] w_bit_field_read_data;
wire [31:0] w_bit_field_value;
`rggen_tie_off_unused_signals(32, 32'h00000003, w_bit_field_read_data, w_bit_field_value)
rggen_default_register #(
.READABLE (1),
.WRITABLE (1),
.ADDRESS_WIDTH (8),
.OFFSET_ADDRESS (8'h00),
.BUS_WIDTH (32),
.DATA_WIDTH (32),
.VALID_BITS (32'h00000003),
.REGISTER_INDEX (0)
) u_register (
.i_clk (i_clk),
Expand Down Expand Up @@ -205,14 +205,14 @@ module csr_dma #(
wire [31:0] w_bit_field_write_data;
wire [31:0] w_bit_field_read_data;
wire [31:0] w_bit_field_value;
`rggen_tie_off_unused_signals(32, 32'h0003ffff, w_bit_field_read_data, w_bit_field_value)
rggen_default_register #(
.READABLE (1),
.WRITABLE (0),
.ADDRESS_WIDTH (8),
.OFFSET_ADDRESS (8'h04),
.BUS_WIDTH (32),
.DATA_WIDTH (32),
.VALID_BITS (32'h0003ffff),
.REGISTER_INDEX (0)
) u_register (
.i_clk (i_clk),
Expand All @@ -234,57 +234,57 @@ module csr_dma #(
.i_bit_field_read_data (w_bit_field_read_data),
.i_bit_field_value (w_bit_field_value)
);
if (1) begin : g_done
if (1) begin : g_version
rggen_bit_field #(
.WIDTH (1),
.WIDTH (16),
.STORAGE (0),
.EXTERNAL_READ_DATA (1),
.TRIGGER (0)
.EXTERNAL_READ_DATA (1)
) u_bit_field (
.i_clk (i_clk),
.i_rst_n (i_rst_n),
.i_clk (1'b0),
.i_rst_n (1'b0),
.i_sw_valid (w_bit_field_valid),
.i_sw_read_mask (w_bit_field_read_mask[0+:1]),
.i_sw_read_mask (w_bit_field_read_mask[0+:16]),
.i_sw_write_enable (1'b0),
.i_sw_write_mask (w_bit_field_write_mask[0+:1]),
.i_sw_write_data (w_bit_field_write_data[0+:1]),
.o_sw_read_data (w_bit_field_read_data[0+:1]),
.o_sw_value (w_bit_field_value[0+:1]),
.i_sw_write_mask (w_bit_field_write_mask[0+:16]),
.i_sw_write_data (w_bit_field_write_data[0+:16]),
.o_sw_read_data (w_bit_field_read_data[0+:16]),
.o_sw_value (w_bit_field_value[0+:16]),
.o_write_trigger (),
.o_read_trigger (),
.i_hw_write_enable (1'b0),
.i_hw_write_data ({1{1'b0}}),
.i_hw_set ({1{1'b0}}),
.i_hw_clear ({1{1'b0}}),
.i_value (i_dma_status_done),
.i_mask ({1{1'b1}}),
.i_hw_write_data ({16{1'b0}}),
.i_hw_set ({16{1'b0}}),
.i_hw_clear ({16{1'b0}}),
.i_value (`rggen_slice(16'hcafe, 16, 0)),
.i_mask ({16{1'b1}}),
.o_value (),
.o_value_unmasked ()
);
end
if (1) begin : g_version
if (1) begin : g_done
rggen_bit_field #(
.WIDTH (16),
.WIDTH (1),
.STORAGE (0),
.EXTERNAL_READ_DATA (1)
.EXTERNAL_READ_DATA (1),
.TRIGGER (0)
) u_bit_field (
.i_clk (1'b0),
.i_rst_n (1'b0),
.i_clk (i_clk),
.i_rst_n (i_rst_n),
.i_sw_valid (w_bit_field_valid),
.i_sw_read_mask (w_bit_field_read_mask[1+:16]),
.i_sw_read_mask (w_bit_field_read_mask[16+:1]),
.i_sw_write_enable (1'b0),
.i_sw_write_mask (w_bit_field_write_mask[1+:16]),
.i_sw_write_data (w_bit_field_write_data[1+:16]),
.o_sw_read_data (w_bit_field_read_data[1+:16]),
.o_sw_value (w_bit_field_value[1+:16]),
.i_sw_write_mask (w_bit_field_write_mask[16+:1]),
.i_sw_write_data (w_bit_field_write_data[16+:1]),
.o_sw_read_data (w_bit_field_read_data[16+:1]),
.o_sw_value (w_bit_field_value[16+:1]),
.o_write_trigger (),
.o_read_trigger (),
.i_hw_write_enable (1'b0),
.i_hw_write_data ({16{1'b0}}),
.i_hw_set ({16{1'b0}}),
.i_hw_clear ({16{1'b0}}),
.i_value (`rggen_slice(16'hcafe, 16, 0)),
.i_mask ({16{1'b1}}),
.i_hw_write_data ({1{1'b0}}),
.i_hw_set ({1{1'b0}}),
.i_hw_clear ({1{1'b0}}),
.i_value (i_dma_status_done),
.i_mask ({1{1'b1}}),
.o_value (),
.o_value_unmasked ()
);
Expand Down Expand Up @@ -325,14 +325,14 @@ module csr_dma #(
wire [63:0] w_bit_field_write_data;
wire [63:0] w_bit_field_read_data;
wire [63:0] w_bit_field_value;
`rggen_tie_off_unused_signals(64, 64'h00000007ffffffff, w_bit_field_read_data, w_bit_field_value)
rggen_default_register #(
.READABLE (1),
.WRITABLE (0),
.ADDRESS_WIDTH (8),
.OFFSET_ADDRESS (8'h08),
.BUS_WIDTH (32),
.DATA_WIDTH (64),
.VALID_BITS (64'h00000007ffffffff),
.REGISTER_INDEX (0)
) u_register (
.i_clk (i_clk),
Expand Down Expand Up @@ -476,14 +476,14 @@ module csr_dma #(
wire [127:0] w_bit_field_write_data;
wire [127:0] w_bit_field_read_data;
wire [127:0] w_bit_field_value;
`rggen_tie_off_unused_signals(128, 128'h00000007ffffffffffffffffffffffff, w_bit_field_read_data, w_bit_field_value)
rggen_default_register #(
.READABLE (1),
.WRITABLE (1),
.ADDRESS_WIDTH (8),
.OFFSET_ADDRESS (8'h10),
.BUS_WIDTH (32),
.DATA_WIDTH (128),
.VALID_BITS (128'h00000007ffffffffffffffffffffffff),
.REGISTER_INDEX (i)
) u_register (
.i_clk (i_clk),
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6 changes: 3 additions & 3 deletions csr_out/csr_dma_ral_pkg.sv
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Expand Up @@ -15,15 +15,15 @@ package csr_dma_ral_pkg;
endfunction
endclass
class dma_status_reg_model extends rggen_ral_reg;
rand rggen_ral_field done;
rand rggen_ral_field version;
rand rggen_ral_field done;
rand rggen_ral_field error;
function new(string name);
super.new(name, 32, 0);
endfunction
function void build();
`rggen_ral_create_field(done, 0, 1, "RO", 1, 1'h0, 1, -1, "")
`rggen_ral_create_field(version, 1, 16, "RO", 0, 16'hcafe, 1, -1, "")
`rggen_ral_create_field(version, 0, 16, "RO", 0, 16'hcafe, 1, -1, "")
`rggen_ral_create_field(done, 16, 1, "RO", 1, 1'h0, 1, -1, "")
`rggen_ral_create_field(error, 17, 1, "RO", 1, 1'h0, 1, -1, "dma_error.error_trig")
endfunction
endclass
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