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minor fixes
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mrcodetastic committed Jul 21, 2024
1 parent 04a1727 commit 95cda9d
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Showing 2 changed files with 16 additions and 22 deletions.
22 changes: 8 additions & 14 deletions src/platforms/esp32c6/dma_parallel_io.cpp
Original file line number Diff line number Diff line change
@@ -1,7 +1,10 @@
#include "dma_parallel_io.hpp"
#include <Arduino.h>

#ifdef CONFIG_IDF_TARGET_ESP32C6

#pragma message "Compiling for ESP32-C6"

//First implementation might have a lot of bugs, especially on deleting and reloading

//major test setup:
Expand Down Expand Up @@ -33,8 +36,6 @@
// for a view clocks




// limitation of parlio interface
// PARLIO_LL_TX_MAX_BITS_PER_FRAME = (PARLIO_LL_TX_MAX_BYTES_PER_FRAME * 8)
// PARLIO_LL_TX_MAX_BYTES_PER_FRAME = 0xFFFF
Expand All @@ -53,8 +54,6 @@
// I don't get it




#pragma message "Compiling for ESP32-C6"

#ifdef ARDUINO_ARCH_ESP32
Expand All @@ -81,22 +80,17 @@ DRAM_ATTR volatile bool previousBufferFree = true;
IRAM_ATTR bool gdma_on_trans_eof_callback(gdma_channel_handle_t dma_chan,
gdma_event_data_t *event_data, void *user_data)
{

//esp_rom_delay_us(100);

previousBufferFree = true;


//parlio_ll_tx_reset_fifo(&PARL_IO);
parlio_ll_tx_reset_clock(&PARL_IO);

//gdma_start(dma_chan, (intptr_t)&_dmadesc_a[0]);

//while (parlio_ll_tx_is_ready(&PARL_IO) == false);

//parlio_ll_tx_start(&PARL_IO, true);
//parlio_ll_tx_enable_clock(&PARL_IO, true);

return true;
}

Expand All @@ -110,28 +104,28 @@ void Bus_Parallel16::config(const config_t &cfg)

bool Bus_Parallel16::init(void)
{
ESP_LOGI("ESP32-C6", "Performing DMA bus init() for ESP-C6");

periph_module_enable(PERIPH_PARLIO_MODULE);
periph_module_reset(PERIPH_PARLIO_MODULE);
periph_module_reset (PERIPH_PARLIO_MODULE);

// Reset LCD bus
parlio_ll_tx_reset_fifo(&PARL_IO);
esp_rom_delay_us(1000);

parlio_ll_clock_source_t clk_src = (parlio_ll_clock_source_t)PARLIO_CLK_SRC_DEFAULT;
uint32_t periph_src_clk_hz = 0;

esp_clk_tree_src_get_freq_hz((soc_module_clk_t)clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &periph_src_clk_hz);
parlio_ll_tx_set_clock_source(&PARL_IO, clk_src);

uint32_t div = (periph_src_clk_hz + _cfg.bus_freq - 1) / _cfg.bus_freq;
parlio_ll_tx_set_clock_div(&PARL_IO, div);
_cfg.bus_freq = periph_src_clk_hz / div;


ESP_LOGI("C6", "Clock divider is %d", (int)div);
ESP_LOGD("C6", "Resulting output clock frequency: %d Mhz", (int)(160000000L / _cfg.bus_freq));




// Allocate DMA channel and connect it to the LCD peripheral
static gdma_channel_alloc_config_t dma_chan_config = {
Expand Down
16 changes: 8 additions & 8 deletions src/platforms/esp32s3/gdma_lcd_parallel16.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -99,7 +99,7 @@
//LCD_CAM.lcd_clock.clk_en = 0; // Enable peripheral clock

// LCD_CAM_LCD_CLK_SEL Select LCD module source clock. 0: clock source is disabled. 1: XTAL_CLK. 2: PLL_D2_CLK. 3: PLL_F160M_CLK. (R/W)
LCD_CAM.lcd_clock.lcd_clk_sel = 3; // Use 160Mhz Clock Source
LCD_CAM.lcd_clock.lcd_clk_sel = 3; // Use 160Mhz Clock Source -> PLL_F160M_CLK

LCD_CAM.lcd_clock.lcd_ck_out_edge = 0; // PCLK low in 1st half cycle
LCD_CAM.lcd_clock.lcd_ck_idle_edge = 0; // PCLK low idle
Expand Down Expand Up @@ -127,20 +127,20 @@
//LCD_CAM.lcd_clock.lcd_clkm_div_num = 10; //16mhz is the fasted the Octal PSRAM can support it seems from faptastic's testing using an N8R8 variant (Octal SPI PSRAM).

// https://github.com/mrfaptastic/ESP32-HUB75-MatrixPanel-DMA/issues/441#issuecomment-1513631890
LCD_CAM.lcd_clock.lcd_clkm_div_num = 12; // 13Mhz is the fastest when the DMA memory is needed to service other peripherals as well.
LCD_CAM.lcd_clock.lcd_clkm_div_num = 12; // 13Mhz is about the fastest output from PSRAM if we want to be able to service other peripherals as well.
}
else
{

auto freq = (_cfg.bus_freq);

auto _div_num = 8; // 20Mhz
auto _div_num = 20; // 8Mhzhz
if (freq < 20000000L) {
_div_num = 12; // 13Mhz
}
else if (freq > 20000000L) {
_div_num = 6; // 26Mhz --- likely to have noise without a good connection
_div_num = 10; // 16Mhz
} else {
_div_num = 7; // 22Mhz --- likely to have noise without a good connection
}

_div_num = 6;

//LCD_CAM.lcd_clock.lcd_clkm_div_num = lcd_clkm_div_num;
LCD_CAM.lcd_clock.lcd_clkm_div_num = _div_num; //3;
Expand Down

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