hypervisor: mshv: relax the requirement for instruction emulation

Previously we required the hypervisor to give us a valid instruction stream. That worked well enough because we never hit any edge conditions (such as when the instruction stream crosses page boundary). Now that MSHV can deal with partial or empty instruction stream, we can remove that requirement. Signed-off-by: Wei Liu <[email protected]>
michael2012z · Jul 4, 2024 · 519476e · 519476e
1 parent 5fec858
commit 519476e
Showing 1 changed file with 4 additions and 2 deletions.
diff --git a/hypervisor/src/mshv/mod.rs b/hypervisor/src/mshv/mod.rs
@@ -641,7 +641,6 @@ impl cpu::Vcpu for MshvVcpu {
                 hv_message_type_HVMSG_UNMAPPED_GPA => {
                     let info = x.to_memory_info().unwrap();
                     let insn_len = info.instruction_byte_count as usize;
-                    assert!(insn_len > 0 && insn_len <= 16);
 
                     let mut context = MshvEmulatorContext {
                         vcpu: self,
@@ -653,7 +652,10 @@ impl cpu::Vcpu for MshvVcpu {
 
                     // Emulate the trapped instruction, and only the first one.
                     let new_state = emul
-                        .emulate_first_insn(self.vp_index as usize, &info.instruction_bytes)
+                        .emulate_first_insn(
+                            self.vp_index as usize,
+                            &info.instruction_bytes[..insn_len],
+                        )
                         .map_err(|e| cpu::HypervisorCpuError::RunVcpu(e.into()))?;
 
                     // Set CPU state back.