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Fixes PathFInder
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masfiyan committed Oct 25, 2023
1 parent 9919c08 commit 6acc8fa
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Showing 3 changed files with 24 additions and 10 deletions.
8 changes: 4 additions & 4 deletions README.md
Original file line number Diff line number Diff line change
Expand Up @@ -87,13 +87,13 @@ Streaming_matrix = [(1, 2, 3, 0)]
| Source | destination | Muxex |
|--------|-------------|-------|
| 1 | 1 | 0 |
| 1 | 3 | 14 |
| 1 | 2 | 15 |
| 1 | 3 | 3 |
| 1 | 2 | 2 |
| 1 | 1 | 0 |
| 2 | 7 | 11 |
| 2 | 7 | 0 |
| -- | -- | -- |
| -- | -- | -- |
| 3 | 4 | 15 |
| 3 | 4 | 1 |
| 3 | 3 | 0 |
#### WaveForm
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4 changes: 2 additions & 2 deletions src/main/scala/components/Muxes.scala
Original file line number Diff line number Diff line change
Expand Up @@ -45,11 +45,11 @@ class Muxes(implicit val config: MagmasiConfig) extends Module{
when ((io.mat1(j)(i) =/= 0.U) && (io.mat2(i) =/= 0.U)) {

when(io.counterMatrix1(j)(i) < io.counterMatrix2(i)){
mux(counter) := (io.mat2(i) - 1.U) - (io.mat1(j)(i) - 1.U)
mux(counter) := (io.counterMatrix2(i) - 1.U) - (io.counterMatrix1(j)(i) - 1.U)
src(counter) := io.mat2(i)
dest(counter) := io.mat1(j)(i)
}.otherwise{
mux(counter) := (io.mat1(j)(i) - 1.U) - (io.mat2(i) - 1.U)
mux(counter) := (io.counterMatrix1(j)(i) - 1.U) - (io.counterMatrix2(i) - 1.U)
src(counter) := io.mat2(i)
dest(counter) := io.mat1(j)(i)
}
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22 changes: 18 additions & 4 deletions src/main/scala/components/SourceDestination.scala
Original file line number Diff line number Diff line change
Expand Up @@ -35,6 +35,7 @@ class SourceDestination(implicit val config: MagmasiConfig) extends Module {
val valid1 = RegInit(false.B)
val jValid = Reg(Bool())
jValid := 0.B
val kvalid = Reg(Bool())
val k = RegInit(0.U(32.W))

val counter1 = RegInit(1.U(32.W))
Expand All @@ -56,15 +57,28 @@ class SourceDestination(implicit val config: MagmasiConfig) extends Module {
}

when (io.Streaming_matrix(k) =/= 0.U) {
counterRegs2(k) := counter2
counter2 := counter2 + 1.U
when (counter2 < (config.NUM_PES + 1).U) {
counterRegs2(k) := counter1
when (~((j === (config.MaxCols - 1).U) && (i === (config.MaxRows - 1).U))){
counter2 := counter2 + 1.U
}
}
}
val reg_i = RegNext(((j === (config.MaxCols - 1).U) && (i === (config.MaxRows - 1).U)), 1.B)
valid1 := Mux(((j === (config.MaxCols - 1).U) && (i === (config.MaxRows - 1).U)) === reg_i,1.B,0.B)

when (k >= 0.U){
k := k + 1.U

// when ((k >= 0.U) && (kvalid === 0.B)){
// k := k + 1.U
// }

when(k === (config.MaxRows - 1).U){
kvalid := 1.B
}.elsewhen((k >= 0.U) && (kvalid === 0.B)){
kvalid := 0.B
k := k + 1.U
}

when (jValid === 0.B){
when(j < (config.MaxCols - 1).U) {
j := j + 1.U
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