Merge pull request #12 from zeeshanrafique23/main

FPU tests passing 133/143.
merledu · Nov 17, 2021 · 7a9ffe8 · 7a9ffe8
2 parents f2664a3 + eb063c6
commit 7a9ffe8
Show file tree

Hide file tree

Showing 19 changed files with 635 additions and 122 deletions.
diff --git a/.gitignore b/.gitignore
@@ -3,4 +3,5 @@ build/
 *.vcd
 fusesoc.conf
 html
-Bender.lock
+Bender.lock
+.vscode/
diff --git a/hw/ip/prim/fpv/prim_esc_rxtx_fpv.core b/hw/ip/prim/fpv/prim_esc_rxtx_fpv.core
@@ -18,7 +18,7 @@ targets:
   default: &default_target
     # note, this setting is just used
     # to generate a file list for jg
-    formal: icarus
+    default_tool: icarus
     filesets:
       - files_formal
     toplevel:

diff --git a/hw/vendor/lowrisc_ibex/dv/riscv_compliance/ibex_riscv_compliance.core b/hw/vendor/lowrisc_ibex/dv/riscv_compliance/ibex_riscv_compliance.core
@@ -69,7 +69,7 @@ parameters:
   WritebackStage:
     datatype: int
     paramtype: vlogparam
-    default: 0
+    default: 1
     description: "Enables third pipeline stage (EXPERIMENTAL)"
 
   BranchPredictor:
@@ -145,3 +145,4 @@ targets:
           - '-Wno-INCABSPATH'
           - "-Wno-IMPERFECTSCH"
           - "-Wno-LITENDIAN"
+          - "-Wno-LATCH"
diff --git a/hw/vendor/lowrisc_ibex/examples/simple_system/ibex_simple_system.core b/hw/vendor/lowrisc_ibex/examples/simple_system/ibex_simple_system.core
@@ -77,7 +77,7 @@ parameters:
   WritebackStage:
     datatype: int
     paramtype: vlogparam
-    default: 0
+    default: 1
     description: "Enables third pipeline stage (EXPERIMENTAL)"
 
   SecureIbex:
@@ -109,6 +109,12 @@ parameters:
     default: 4
     paramtype: vlogparam
     description: "Number of PMP regions"
+
+  RVF:
+    datatype: str
+    default: ibex_pkg::RV32FSingle
+    paramtype: vlogdefine
+    description: "Used to enable the F or D extension with ibex, possible values: ibex_pkg::RV32FDNone, ibex_pkg::RV32FSingle, ibex_pkg::RV32DDouble"
 
 targets:
   default: &default_target
@@ -122,6 +128,7 @@ targets:
       - RV32M
       - RV32B
       - RegFile
+      - RVF
       - ICache
       - ICacheECC
       - BranchTargetALU
@@ -176,3 +183,5 @@ targets:
           - '-Wno-UNOPTFLAT'
           - '-Wno-INCABSPATH'
           - "-Wno-IMPERFECTSCH"
+          - "-Wno-LATCH"
+          - "-Wno-LITENDIAN"
diff --git a/hw/vendor/lowrisc_ibex/examples/simple_system/rtl/ibex_simple_system.sv b/hw/vendor/lowrisc_ibex/examples/simple_system/rtl/ibex_simple_system.sv
@@ -18,6 +18,10 @@
   `define RegFile ibex_pkg::RegFileFF
 `endif
 
+`ifndef RVF
+  `define RVF ibex_pkg::RV32FSingle
+`endif
+
 /**
  * Ibex simple system
  *
@@ -43,8 +47,9 @@ module ibex_simple_system (
   parameter ibex_pkg::rv32m_e   RV32M                    = `RV32M;
   parameter ibex_pkg::rv32b_e   RV32B                    = `RV32B;
   parameter ibex_pkg::regfile_e RegFile                  = `RegFile;
+  parameter ibex_pkg::rvfloat_e RVF                      = `RVF;
   parameter bit                 BranchTargetALU          = 1'b0;
-  parameter bit                 WritebackStage           = 1'b0;
+  parameter bit                 WritebackStage           = 1'b1;
   parameter bit                 ICache                   = 1'b0;
   parameter bit                 ICacheECC                = 1'b0;
   parameter bit                 BranchPredictor          = 1'b0;
@@ -170,6 +175,7 @@ module ibex_simple_system (
       .RV32E           ( RV32E           ),
       .RV32M           ( RV32M           ),
       .RV32B           ( RV32B           ),
+      .RVF             ( RVF             ),
       .RegFile         ( RegFile         ),
       .BranchTargetALU ( BranchTargetALU ),
       .ICache          ( ICache          ),

diff --git a/hw/vendor/lowrisc_ibex/rtl/ibex_compressed_decoder.sv b/hw/vendor/lowrisc_ibex/rtl/ibex_compressed_decoder.sv
@@ -56,18 +56,29 @@ module ibex_compressed_decoder (
                        2'b00, 2'b01, instr_i[9:7], 3'b010, 2'b01, instr_i[4:2], {OPCODE_LOAD}};
           end
 
+          3'b011: begin
+            // c.flw -> flw frd`, imm(rs1)
+            instr_o = {5'b0, instr_i[5], instr_i[12:10], instr_i[6],
+                       2'b00, 2'b01, instr_i[9:7], 3'b010, 2'b01, instr_i[4:2], {OPCODE_LOAD_FP}};
+          end
+
           3'b110: begin
             // c.sw -> sw rs2', imm(rs1')
             instr_o = {5'b0, instr_i[5], instr_i[12], 2'b01, instr_i[4:2],
                        2'b01, instr_i[9:7], 3'b010, instr_i[11:10], instr_i[6],
                        2'b00, {OPCODE_STORE}};
           end
 
+          3'b111: begin
+            // c.fsw -> fsw frs2`, imm(rs1`)
+            instr_o = {5'b0, instr_i[5], instr_i[12], 2'b01, instr_i[4:2],
+                       2'b01, instr_i[9:7], 3'b010, instr_i[11:10], instr_i[6],
+                       2'b00, {OPCODE_STORE_FP}};
+          end
+
           3'b001,
-          3'b011,
           3'b100,
-          3'b101,
-          3'b111: begin
+          3'b101: begin
             illegal_instr_o = 1'b1;
           end
 
@@ -220,6 +231,12 @@ module ibex_compressed_decoder (
             if (instr_i[11:7] == 5'b0)  illegal_instr_o = 1'b1;
           end
 
+          3'b011: begin
+            // c.flwsp -> flw frd, imm(x2)
+            instr_o = {4'b0, instr_i[3:2], instr_i[12], instr_i[6:4], 2'b00, 5'h02,
+                       3'b010, instr_i[11:7], OPCODE_LOAD_FP};
+          end
+
           3'b100: begin
             if (instr_i[12] == 1'b0) begin
               if (instr_i[6:2] != 5'b0) begin
@@ -254,10 +271,14 @@ module ibex_compressed_decoder (
                        instr_i[11:9], 2'b00, {OPCODE_STORE}};
           end
 
-          3'b001,
-          3'b011,
-          3'b101,
           3'b111: begin
+            // c.fswsp -> fsw frs2, imm(x2)
+            instr_o = {4'b0, instr_i[8:7], instr_i[12], instr_i[6:2], 5'h02, 3'b010,
+                       instr_i[11:9], 2'b00, {OPCODE_STORE_FP}};
+          end
+
+          3'b001,
+          3'b101: begin
             illegal_instr_o = 1'b1;
           end