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Audio adjustments
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Added joystick key mapping
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@mdovey
mdovey committed Dec 29, 2021
1 parent 4cae26a commit a603c01
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Showing 600 changed files with 127,862 additions and 194,129 deletions.
636 changes: 408 additions & 228 deletions ip/zxaudio/component.xml
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100 changes: 10 additions & 90 deletions ip/zxaudio/sim/audio.v
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Original file line number Diff line number Diff line change
@@ -1,20 +1,20 @@
//Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
//Date : Tue Dec 21 12:12:24 2021
//Date : Wed Dec 29 09:01:01 2021
//Host : AW13R3 running 64-bit major release (build 9200)
//Command : generate_target audio.bd
//Design : audio
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* CORE_GENERATION_INFO = "audio,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=audio,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=21,numReposBlks=21,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=21,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}" *) (* HW_HANDOFF = "audio.hwdef" *)
(* CORE_GENERATION_INFO = "audio,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=audio,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=13,numReposBlks=13,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=13,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}" *) (* HW_HANDOFF = "audio.hwdef" *)
module audio
(audio_left,
(aud_sd,
audio_left,
audio_pwm,
audio_right,
audio_sd,
clk_audio,
clk_peripheral,
linein_lrck,
Expand All @@ -29,12 +29,11 @@ module audio
reset,
tape_ear,
tape_mic,
tape_pwm,
tape_sd);
tape_pwm);
output aud_sd;
input [12:0]audio_left;
output audio_pwm;
input [12:0]audio_right;
output audio_sd;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.CLK_AUDIO CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.CLK_AUDIO, CLK_DOMAIN audio_clk_audio, FREQ_HZ 12280700, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0" *) input clk_audio;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.CLK_PERIPHERAL CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.CLK_PERIPHERAL, CLK_DOMAIN audio_clk_peripheral, FREQ_HZ 28000000, FREQ_TOLERANCE_HZ 0, INSERT_VIP 0, PHASE 0.0" *) input clk_peripheral;
output linein_lrck;
Expand All @@ -50,35 +49,16 @@ module audio
output tape_ear;
input tape_mic;
output tape_pwm;
output tape_sd;

wire [15:0]IIR_filter_0_output_l;
wire [15:0]IIR_filter_0_output_r;
wire [39:0]audio_filter_control_0_cx;
wire [7:0]audio_filter_control_0_cx0;
wire [7:0]audio_filter_control_0_cx1;
wire [7:0]audio_filter_control_0_cx2;
wire [23:0]audio_filter_control_0_cy0;
wire [23:0]audio_filter_control_0_cy1;
wire [23:0]audio_filter_control_0_cy2;
wire audio_filter_control_0_dc_ce;
wire audio_filter_control_0_dc_mute;
wire audio_filter_control_0_dc_sample_rate;
wire audio_filter_control_0_iir_ce;
wire audio_filter_control_0_iir_sample_ce;
wire [12:0]audio_left_1;
wire [15:0]audio_mono_0_mono_out;
wire [15:0]audio_mono_1_mono_out;
wire [15:0]audio_prefilter_0_dout;
wire [15:0]audio_prefilter_1_dout;
wire audio_psg_0_psg_en;
wire audio_reset_0_rst;
wire audio_reset_0_rstn;
wire [12:0]audio_right_1;
wire [15:0]audio_scaler_0_dout;
wire [15:0]audio_scaler_0_dout1;
wire [15:0]audio_scaler_1_dout;
wire [15:0]audio_scaler_1_dout1;
wire [12:0]audio_sync_0_dout;
wire [12:0]audio_sync_1_dout;
wire clk_audio_1;
Expand All @@ -95,13 +75,11 @@ module audio
wire tape_ear_0_ear;
wire [15:0]tape_mic_0_dout;
wire tape_mic_1;
wire [15:0]twos_complement_0_dout;
wire [15:0]twos_complement_1_dout;

assign aud_sd = audio_reset_0_rstn;
assign audio_left_1 = audio_left[12:0];
assign audio_pwm = sigma_delta_dac_0_DACout;
assign audio_right_1 = audio_right[12:0];
assign audio_sd = audio_reset_0_rstn;
assign clk_audio_1 = clk_audio;
assign clk_peripheral_1 = clk_peripheral;
assign linein_lrck = i2s_transceiver_0_ws;
Expand All @@ -117,52 +95,6 @@ module audio
assign tape_ear = tape_ear_0_ear;
assign tape_mic_1 = tape_mic;
assign tape_pwm = sigma_delta_dac_1_DACout;
assign tape_sd = audio_reset_0_rstn;
audio_DC_blocker_0_0 DC_blocker_0
(.ce(audio_filter_control_0_dc_ce),
.clk(clk_audio_1),
.din(IIR_filter_0_output_l),
.dout(audio_scaler_0_dout),
.mute(audio_filter_control_0_dc_mute),
.sample_rate(audio_filter_control_0_dc_sample_rate));
audio_DC_blocker_1_0 DC_blocker_1
(.ce(audio_filter_control_0_dc_ce),
.clk(clk_audio_1),
.din(IIR_filter_0_output_r),
.dout(audio_scaler_1_dout),
.mute(audio_filter_control_0_dc_mute),
.sample_rate(audio_filter_control_0_dc_sample_rate));
audio_IIR_filter_0_0 IIR_filter_0
(.ce(audio_filter_control_0_iir_ce),
.clk(clk_audio_1),
.cx(audio_filter_control_0_cx),
.cx0(audio_filter_control_0_cx0),
.cx1(audio_filter_control_0_cx1),
.cx2(audio_filter_control_0_cx2),
.cy0(audio_filter_control_0_cy0),
.cy1(audio_filter_control_0_cy1),
.cy2(audio_filter_control_0_cy2),
.input_l(twos_complement_0_dout),
.input_r(twos_complement_1_dout),
.output_l(IIR_filter_0_output_l),
.output_r(IIR_filter_0_output_r),
.reset(audio_reset_0_rst),
.sample_ce(audio_filter_control_0_iir_sample_ce));
audio_audio_filter_control_0_0 audio_filter_control_0
(.clk(clk_audio_1),
.cx(audio_filter_control_0_cx),
.cx0(audio_filter_control_0_cx0),
.cx1(audio_filter_control_0_cx1),
.cx2(audio_filter_control_0_cx2),
.cy0(audio_filter_control_0_cy0),
.cy1(audio_filter_control_0_cy1),
.cy2(audio_filter_control_0_cy2),
.dc_ce(audio_filter_control_0_dc_ce),
.dc_mute(audio_filter_control_0_dc_mute),
.dc_sample_rate(audio_filter_control_0_dc_sample_rate),
.iir_ce(audio_filter_control_0_iir_ce),
.iir_sample_ce(audio_filter_control_0_iir_sample_ce),
.reset(audio_reset_0_rst));
audio_audio_mono_0_0 audio_mono_0
(.left_in(audio_scaler_0_dout),
.mono_out(audio_mono_0_mono_out),
Expand All @@ -171,12 +103,6 @@ module audio
(.left_in(i2s_transceiver_0_l_data_rx),
.mono_out(audio_mono_1_mono_out),
.right_in(i2s_transceiver_0_r_data_rx));
audio_audio_prefilter_0_0 audio_prefilter_0
(.din(audio_scaler_0_dout1),
.dout(audio_prefilter_0_dout));
audio_audio_prefilter_1_0 audio_prefilter_1
(.din(audio_scaler_1_dout1),
.dout(audio_prefilter_1_dout));
audio_audio_psg_0_0 audio_psg_0
(.clk_peripheral(clk_peripheral_1),
.psg_en(audio_psg_0_psg_en));
Expand All @@ -187,15 +113,15 @@ module audio
.rstn(audio_reset_0_rstn));
audio_audio_scaler_0_0 audio_scaler_0
(.din(audio_sync_0_dout),
.dout(audio_scaler_0_dout1));
.dout(audio_scaler_0_dout));
audio_audio_scaler_1_0 audio_scaler_1
(.din(audio_sync_1_dout),
.dout(audio_scaler_1_dout1));
.dout(audio_scaler_1_dout));
audio_audio_sync_0_0 audio_sync_0
(.clk(clk_audio_1),
.din(audio_left_1),
.dout(audio_sync_0_dout));
audio_audio_sync_1_0 audio_sync_1
audio_audio_sync_0_1 audio_sync_1
(.clk(clk_audio_1),
.din(audio_right_1),
.dout(audio_sync_1_dout));
Expand Down Expand Up @@ -227,10 +153,4 @@ module audio
audio_tape_mic_0_0 tape_mic_0
(.din(tape_mic_1),
.dout(tape_mic_0_dout));
audio_twos_complement_0_0 twos_complement_0
(.din(audio_prefilter_0_dout),
.dout(twos_complement_0_dout));
audio_twos_complement_1_0 twos_complement_1
(.din(audio_prefilter_1_dout),
.dout(twos_complement_1_dout));
endmodule
3 changes: 2 additions & 1 deletion ip/zxaudio/sim/audio_audio_mono_0_0.v
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Original file line number Diff line number Diff line change
Expand Up @@ -65,7 +65,8 @@ input wire [15 : 0] right_in;
output wire [15 : 0] mono_out;

audio_mono #(
.AUDIO_DW(16)
.AUDIO_DW(16),
.SHIFT(1)
) inst (
.left_in(left_in),
.right_in(right_in),
Expand Down
3 changes: 2 additions & 1 deletion ip/zxaudio/sim/audio_audio_mono_1_0.v
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Original file line number Diff line number Diff line change
Expand Up @@ -65,7 +65,8 @@ input wire [15 : 0] right_in;
output wire [15 : 0] mono_out;

audio_mono #(
.AUDIO_DW(16)
.AUDIO_DW(16),
.SHIFT(1)
) inst (
.left_in(left_in),
.right_in(right_in),
Expand Down
2 changes: 1 addition & 1 deletion ...ilter_0_0/sim/audio_audio_prefilter_0_0.v → ip/zxaudio/sim/audio_audio_prefilter_0_1.v
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Original file line number Diff line number Diff line change
Expand Up @@ -54,7 +54,7 @@

(* IP_DEFINITION_SOURCE = "module_ref" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module audio_audio_prefilter_0_0 (
module audio_audio_prefilter_0_1 (
din,
dout
);
Expand Down
2 changes: 1 addition & 1 deletion ...audio_sync_1_0/sim/audio_audio_sync_1_0.v → ip/zxaudio/sim/audio_audio_sync_0_1.v
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Original file line number Diff line number Diff line change
Expand Up @@ -54,7 +54,7 @@

(* IP_DEFINITION_SOURCE = "module_ref" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module audio_audio_sync_1_0 (
module audio_audio_sync_0_1 (
din,
dout,
clk
Expand Down
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