Adjusted status LED brightness

mdovey · Jan 1, 2022 · 8c5866d · 8c5866d
1 parent 9634e78
commit 8c5866d
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diff --git a/ip/zxnexys_ledsegment/component.xml b/ip/zxnexys_ledsegment/component.xml
@@ -172,7 +172,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>5b9bba2b</spirit:value>
+            <spirit:value>6afc1aa5</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -188,7 +188,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>5b9bba2b</spirit:value>
+            <spirit:value>6afc1aa5</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -469,7 +469,7 @@
       <spirit:file>
         <spirit:name>../../srcs/sources/new/nexys/ledsegment.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_42c96640</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_a8c3f306</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -535,11 +535,11 @@
       </xilinx:taxonomies>
       <xilinx:displayName>zxnexys_ledsegment_v1_3</xilinx:displayName>
       <xilinx:definitionSource>package_project</xilinx:definitionSource>
-      <xilinx:coreRevision>21</xilinx:coreRevision>
+      <xilinx:coreRevision>22</xilinx:coreRevision>
       <xilinx:upgrades>
         <xilinx:canUpgradeFrom>specnext.com:specnext:ledsegment:1.0</xilinx:canUpgradeFrom>
       </xilinx:upgrades>
-      <xilinx:coreCreationDateTime>2021-12-31T22:17:21Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2022-01-01T02:36:49Z</xilinx:coreCreationDateTime>
       <xilinx:tags>
         <xilinx:tag xilinx:name="ui.data.coregen.df@6364bc72_ARCHIVE_LOCATION">v:/ip/zxnexys_ledsegment</xilinx:tag>
         <xilinx:tag xilinx:name="ui.data.coregen.df@45d2eb01_ARCHIVE_LOCATION">v:/ip/zxnexys_ledsegment</xilinx:tag>
@@ -811,12 +811,23 @@
         <xilinx:tag xilinx:name="ui.data.coregen.df@300147af_ARCHIVE_LOCATION">v:/ip/zxnexys_ledsegment</xilinx:tag>
         <xilinx:tag xilinx:name="ui.data.coregen.df@7ce1912a_ARCHIVE_LOCATION">v:/ip/zxnexys_ledsegment</xilinx:tag>
         <xilinx:tag xilinx:name="ui.data.coregen.df@1effc2fa_ARCHIVE_LOCATION">v:/ip/zxnexys_ledsegment</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.df@81dc1f0_ARCHIVE_LOCATION">v:/ip/zxnexys_ledsegment</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.df@3902fe89_ARCHIVE_LOCATION">v:/ip/zxnexys_ledsegment</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.df@77147221_ARCHIVE_LOCATION">v:/ip/zxnexys_ledsegment</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.df@1d98be0_ARCHIVE_LOCATION">v:/ip/zxnexys_ledsegment</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.df@216a91d7_ARCHIVE_LOCATION">v:/ip/zxnexys_ledsegment</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.df@bdbea4a_ARCHIVE_LOCATION">v:/ip/zxnexys_ledsegment</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.df@6a7b39f3_ARCHIVE_LOCATION">v:/ip/zxnexys_ledsegment</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.df@7223d2a8_ARCHIVE_LOCATION">v:/ip/zxnexys_ledsegment</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.df@7c079cde_ARCHIVE_LOCATION">v:/ip/zxnexys_ledsegment</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.df@2a9aaae7_ARCHIVE_LOCATION">v:/ip/zxnexys_ledsegment</xilinx:tag>
+        <xilinx:tag xilinx:name="ui.data.coregen.df@47526978_ARCHIVE_LOCATION">v:/ip/zxnexys_ledsegment</xilinx:tag>
       </xilinx:tags>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
       <xilinx:xilinxVersion>2021.2</xilinx:xilinxVersion>
       <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="f47af03a"/>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="7accfc0b"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="002e8aa2"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="800c0069"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="2432bb96"/>
     </xilinx:packagingInfo>

diff --git a/ip/zxnexys_ledsegment/src/ledsegment.v b/ip/zxnexys_ledsegment/src/ledsegment.v
@@ -170,8 +170,8 @@ always @(posedge cpu_clk, posedge cpu_wait_n)
 rgb rgb16 (
     .clk(clk_peripheral),
     .r(machine_timing[0] ? 3'h4 : 3'h0),
-    .g(machine_timing[1] ? 3'h3 : 3'h0),
-    .b(machine_timing[2] ? 3'h2 : 3'h0),
+    .g(machine_timing[1] ? 3'h2 : 3'h0),
+    .b(machine_timing[2] ? 3'h1 : 3'h0),
     .led_r(led17_r),
     .led_g(led17_g),
     .led_b(led17_b)   
@@ -180,8 +180,8 @@ rgb rgb16 (
 rgb rgb17 (
     .clk(clk_peripheral),
     .r(((memory_resetn && (video_reset || peripheral_reset)) || !(memory_resetn || (video_reset && peripheral_reset)))  ? 3'h4 : 3'h0),
-    .g((!peripheral_reset || !video_reset)                                                                              ? 3'h3 : 3'h0),
-    .b(cpu_wait                                                                                                         ? 3'h2 : 3'h0),
+    .g((!peripheral_reset || !video_reset)                                                                              ? 3'h2 : 3'h0),
+    .b(cpu_wait                                                                                                         ? 3'h1 : 3'h0),
     .led_r(led16_r),
     .led_g(led16_g),
     .led_b(led16_b)   

diff --git a/srcs/sources/bd/zxnexys/hdl/zxnexys_wrapper.v b/srcs/sources/bd/zxnexys/hdl/zxnexys_wrapper.v
@@ -1,7 +1,7 @@
 //Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
 //--------------------------------------------------------------------------------
 //Tool Version: Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
-//Date        : Fri Dec 31 22:34:41 2021
+//Date        : Sat Jan  1 02:44:55 2022
 //Host        : AW13R3 running 64-bit major release  (build 9200)
 //Command     : generate_target zxnexys_wrapper.bd
 //Design      : zxnexys_wrapper

diff --git a/srcs/sources/bd/zxnexys/hw_handoff/zxnexys.hwh b/srcs/sources/bd/zxnexys/hw_handoff/zxnexys.hwh
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Fri Dec 31 22:36:19 2021" VIVADOVERSION="2021.2">
+<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Sat Jan  1 02:46:34 2022" VIVADOVERSION="2021.2">
 
   <SYSTEMINFO ARCH="artix7" BOARD="digilentinc.com:nexys-a7-100t:part0:1.0" DEVICE="7a100t" NAME="zxnexys" PACKAGE="csg324" SPEEDGRADE="-1"/>
 
@@ -5667,7 +5667,7 @@
         </BUSINTERFACE>
       </BUSINTERFACES>
     </MODULE>
-    <MODULE COREREVISION="21" FULLNAME="/zxnexys_ledsegment_0" HWVERSION="1.3" INSTANCE="zxnexys_ledsegment_0" IPTYPE="MONITOR" IS_ENABLE="1" MODCLASS="MONITOR" MODTYPE="zxnexys_ledsegment" VLNV="specnext.com:specnext:zxnexys_ledsegment:1.3">
+    <MODULE COREREVISION="22" FULLNAME="/zxnexys_ledsegment_0" HWVERSION="1.3" INSTANCE="zxnexys_ledsegment_0" IPTYPE="MONITOR" IS_ENABLE="1" MODCLASS="MONITOR" MODTYPE="zxnexys_ledsegment" VLNV="specnext.com:specnext:zxnexys_ledsegment:1.3">
       <DOCUMENTS/>
       <PARAMETERS>
         <PARAMETER NAME="Component_Name" VALUE="zxnexys_zxnexys_ledsegment_0_0"/>

diff --git a/srcs/sources/bd/zxnexys/ip/zxnexys_clk_wiz_0_0/zxnexys_clk_wiz_0_0.dcp b/srcs/sources/bd/zxnexys/ip/zxnexys_clk_wiz_0_0/zxnexys_clk_wiz_0_0.dcp
diff --git a/srcs/sources/bd/zxnexys/ip/zxnexys_clk_wiz_0_0/zxnexys_clk_wiz_0_0.xml b/srcs/sources/bd/zxnexys/ip/zxnexys_clk_wiz_0_0/zxnexys_clk_wiz_0_0.xml
@@ -1780,7 +1780,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Dec 31 22:34:42 UTC 2021</spirit:value>
+            <spirit:value>Sat Jan 01 02:44:56 UTC 2022</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>outputProductCRC</spirit:name>
@@ -1810,7 +1810,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Dec 31 22:34:42 UTC 2021</spirit:value>
+            <spirit:value>Sat Jan 01 02:44:56 UTC 2022</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>outputProductCRC</spirit:name>
@@ -1829,7 +1829,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Dec 31 22:34:42 UTC 2021</spirit:value>
+            <spirit:value>Sat Jan 01 02:44:56 UTC 2022</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>outputProductCRC</spirit:name>
@@ -1848,7 +1848,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Dec 31 22:34:42 UTC 2021</spirit:value>
+            <spirit:value>Sat Jan 01 02:44:56 UTC 2022</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>outputProductCRC</spirit:name>
@@ -1866,7 +1866,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Dec 31 22:34:43 UTC 2021</spirit:value>
+            <spirit:value>Sat Jan 01 02:44:57 UTC 2022</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>outputProductCRC</spirit:name>
@@ -1884,7 +1884,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Dec 31 22:38:58 UTC 2021</spirit:value>
+            <spirit:value>Sat Jan 01 02:49:14 UTC 2022</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>outputProductCRC</spirit:name>

diff --git a/srcs/sources/bd/zxnexys/ip/zxnexys_clk_wiz_0_0/zxnexys_clk_wiz_0_0_sim_netlist.v b/srcs/sources/bd/zxnexys/ip/zxnexys_clk_wiz_0_0/zxnexys_clk_wiz_0_0_sim_netlist.v
@@ -1,7 +1,7 @@
 // Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
 // --------------------------------------------------------------------------------
 // Tool Version: Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
-// Date        : Fri Dec 31 22:38:58 2021
+// Date        : Sat Jan  1 02:49:14 2022
 // Host        : AW13R3 running 64-bit major release  (build 9200)
 // Command     : write_verilog -force -mode funcsim
 //               v:/srcs/sources/bd/zxnexys/ip/zxnexys_clk_wiz_0_0/zxnexys_clk_wiz_0_0_sim_netlist.v

diff --git a/srcs/sources/bd/zxnexys/ip/zxnexys_clk_wiz_0_0/zxnexys_clk_wiz_0_0_sim_netlist.vhdl b/srcs/sources/bd/zxnexys/ip/zxnexys_clk_wiz_0_0/zxnexys_clk_wiz_0_0_sim_netlist.vhdl
@@ -1,7 +1,7 @@
 -- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
 -- --------------------------------------------------------------------------------
 -- Tool Version: Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
--- Date        : Fri Dec 31 22:38:58 2021
+-- Date        : Sat Jan  1 02:49:14 2022
 -- Host        : AW13R3 running 64-bit major release  (build 9200)
 -- Command     : write_vhdl -force -mode funcsim
 --               v:/srcs/sources/bd/zxnexys/ip/zxnexys_clk_wiz_0_0/zxnexys_clk_wiz_0_0_sim_netlist.vhdl

diff --git a/srcs/sources/bd/zxnexys/ip/zxnexys_clk_wiz_0_0/zxnexys_clk_wiz_0_0_stub.v b/srcs/sources/bd/zxnexys/ip/zxnexys_clk_wiz_0_0/zxnexys_clk_wiz_0_0_stub.v
@@ -1,7 +1,7 @@
 // Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
 // --------------------------------------------------------------------------------
 // Tool Version: Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
-// Date        : Fri Dec 31 22:38:58 2021
+// Date        : Sat Jan  1 02:49:14 2022
 // Host        : AW13R3 running 64-bit major release  (build 9200)
 // Command     : write_verilog -force -mode synth_stub
 //               v:/srcs/sources/bd/zxnexys/ip/zxnexys_clk_wiz_0_0/zxnexys_clk_wiz_0_0_stub.v

diff --git a/srcs/sources/bd/zxnexys/ip/zxnexys_clk_wiz_0_0/zxnexys_clk_wiz_0_0_stub.vhdl b/srcs/sources/bd/zxnexys/ip/zxnexys_clk_wiz_0_0/zxnexys_clk_wiz_0_0_stub.vhdl
@@ -1,7 +1,7 @@
 -- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
 -- --------------------------------------------------------------------------------
 -- Tool Version: Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
--- Date        : Fri Dec 31 22:38:58 2021
+-- Date        : Sat Jan  1 02:49:14 2022
 -- Host        : AW13R3 running 64-bit major release  (build 9200)
 -- Command     : write_vhdl -force -mode synth_stub
 --               v:/srcs/sources/bd/zxnexys/ip/zxnexys_clk_wiz_0_0/zxnexys_clk_wiz_0_0_stub.vhdl

diff --git a/srcs/sources/bd/zxnexys/ip/zxnexys_mig_7series_0_0/zxnexys_mig_7series_0_0.dcp b/srcs/sources/bd/zxnexys/ip/zxnexys_mig_7series_0_0/zxnexys_mig_7series_0_0.dcp
diff --git a/srcs/sources/bd/zxnexys/ip/zxnexys_mig_7series_0_0/zxnexys_mig_7series_0_0.xml b/srcs/sources/bd/zxnexys/ip/zxnexys_mig_7series_0_0/zxnexys_mig_7series_0_0.xml
@@ -23472,7 +23472,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Dec 31 22:34:50 UTC 2021</spirit:value>
+            <spirit:value>Sat Jan 01 02:45:07 UTC 2022</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>outputProductCRC</spirit:name>
@@ -23503,7 +23503,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Dec 31 22:34:59 UTC 2021</spirit:value>
+            <spirit:value>Sat Jan 01 02:45:17 UTC 2022</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>outputProductCRC</spirit:name>
@@ -23523,7 +23523,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Dec 31 22:35:07 UTC 2021</spirit:value>
+            <spirit:value>Sat Jan 01 02:45:25 UTC 2022</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>outputProductCRC</spirit:name>
@@ -23543,7 +23543,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Dec 31 22:35:16 UTC 2021</spirit:value>
+            <spirit:value>Sat Jan 01 02:45:34 UTC 2022</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>outputProductCRC</spirit:name>
@@ -23562,7 +23562,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Dec 31 22:35:24 UTC 2021</spirit:value>
+            <spirit:value>Sat Jan 01 02:45:44 UTC 2022</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>outputProductCRC</spirit:name>
@@ -23580,7 +23580,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Dec 31 22:43:27 UTC 2021</spirit:value>
+            <spirit:value>Sat Jan 01 02:53:42 UTC 2022</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>outputProductCRC</spirit:name>

diff --git a/...eries_0_0/zxnexys_mig_7series_0_0/example_design/par/compatible_ucf/xc7a50tcsg324_pkg.xdc b/...eries_0_0/zxnexys_mig_7series_0_0/example_design/par/compatible_ucf/xc7a50tcsg324_pkg.xdc
@@ -1,7 +1,7 @@
 ##################################################################################################
 ## 
 ##  Xilinx, Inc. 2010            www.xilinx.com 
-##  Fri Dec 31 22:35:24 2021
+##  Sat Jan  1 02:45:44 2022
 
 ##  Generated by MIG Version 4.2
 ##  

diff --git a/...xys/ip/zxnexys_mig_7series_0_0/zxnexys_mig_7series_0_0/example_design/par/example_top.xdc b/...xys/ip/zxnexys_mig_7series_0_0/zxnexys_mig_7series_0_0/example_design/par/example_top.xdc
@@ -1,7 +1,7 @@
 ##################################################################################################
 ## 
 ##  Xilinx, Inc. 2010            www.xilinx.com 
-##  Fri Dec 31 22:35:24 2021
+##  Sat Jan  1 02:45:44 2022
 
 ##  Generated by MIG Version 4.2
 ##  

diff --git a/..._0_0/zxnexys_mig_7series_0_0/user_design/constraints/compatible_ucf/xc7a50tcsg324_pkg.xdc b/..._0_0/zxnexys_mig_7series_0_0/user_design/constraints/compatible_ucf/xc7a50tcsg324_pkg.xdc
@@ -1,7 +1,7 @@
 ##################################################################################################
 ## 
 ##  Xilinx, Inc. 2010            www.xilinx.com 
-##  Fri Dec 31 22:35:24 2021
+##  Sat Jan  1 02:45:43 2022
 
 ##  Generated by MIG Version 4.2
 ##  

diff --git a/...g_7series_0_0/zxnexys_mig_7series_0_0/user_design/constraints/zxnexys_mig_7series_0_0.xdc b/...g_7series_0_0/zxnexys_mig_7series_0_0/user_design/constraints/zxnexys_mig_7series_0_0.xdc
@@ -1,7 +1,7 @@
 ##################################################################################################
 ## 
 ##  Xilinx, Inc. 2010            www.xilinx.com 
-##  Fri Dec 31 22:35:24 2021
+##  Sat Jan  1 02:45:43 2022
 
 ##  Generated by MIG Version 4.2
 ##  

diff --git a/...eries_0_0/zxnexys_mig_7series_0_0/user_design/constraints/zxnexys_mig_7series_0_0_ooc.xdc b/...eries_0_0/zxnexys_mig_7series_0_0/user_design/constraints/zxnexys_mig_7series_0_0_ooc.xdc
@@ -9,7 +9,7 @@
 ##################################################################################################
 ## 
 ##  Xilinx, Inc. 2010            www.xilinx.com 
-##  Fri Dec 31 22:35:24 2021
+##  Sat Jan  1 02:45:44 2022
 
 ##  Generated by MIG Version 4.2
 ##  

diff --git a/srcs/sources/bd/zxnexys/ip/zxnexys_mig_7series_0_0/zxnexys_mig_7series_0_0_sim_netlist.v b/srcs/sources/bd/zxnexys/ip/zxnexys_mig_7series_0_0/zxnexys_mig_7series_0_0_sim_netlist.v
@@ -1,7 +1,7 @@
 // Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
 // --------------------------------------------------------------------------------
 // Tool Version: Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
-// Date        : Fri Dec 31 22:43:21 2021
+// Date        : Sat Jan  1 02:53:37 2022
 // Host        : AW13R3 running 64-bit major release  (build 9200)
 // Command     : write_verilog -force -mode funcsim
 //               v:/srcs/sources/bd/zxnexys/ip/zxnexys_mig_7series_0_0/zxnexys_mig_7series_0_0_sim_netlist.v

diff --git a/srcs/sources/bd/zxnexys/ip/zxnexys_mig_7series_0_0/zxnexys_mig_7series_0_0_sim_netlist.vhdl b/srcs/sources/bd/zxnexys/ip/zxnexys_mig_7series_0_0/zxnexys_mig_7series_0_0_sim_netlist.vhdl
@@ -1,7 +1,7 @@
 -- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
 -- --------------------------------------------------------------------------------
 -- Tool Version: Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
--- Date        : Fri Dec 31 22:43:23 2021
+-- Date        : Sat Jan  1 02:53:38 2022
 -- Host        : AW13R3 running 64-bit major release  (build 9200)
 -- Command     : write_vhdl -force -mode funcsim
 --               v:/srcs/sources/bd/zxnexys/ip/zxnexys_mig_7series_0_0/zxnexys_mig_7series_0_0_sim_netlist.vhdl

diff --git a/srcs/sources/bd/zxnexys/ip/zxnexys_mig_7series_0_0/zxnexys_mig_7series_0_0_stub.v b/srcs/sources/bd/zxnexys/ip/zxnexys_mig_7series_0_0/zxnexys_mig_7series_0_0_stub.v
@@ -1,7 +1,7 @@
 // Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
 // --------------------------------------------------------------------------------
 // Tool Version: Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
-// Date        : Fri Dec 31 22:43:21 2021
+// Date        : Sat Jan  1 02:53:37 2022
 // Host        : AW13R3 running 64-bit major release  (build 9200)
 // Command     : write_verilog -force -mode synth_stub
 //               v:/srcs/sources/bd/zxnexys/ip/zxnexys_mig_7series_0_0/zxnexys_mig_7series_0_0_stub.v

diff --git a/srcs/sources/bd/zxnexys/ip/zxnexys_mig_7series_0_0/zxnexys_mig_7series_0_0_stub.vhdl b/srcs/sources/bd/zxnexys/ip/zxnexys_mig_7series_0_0/zxnexys_mig_7series_0_0_stub.vhdl
@@ -1,7 +1,7 @@
 -- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
 -- --------------------------------------------------------------------------------
 -- Tool Version: Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
--- Date        : Fri Dec 31 22:43:21 2021
+-- Date        : Sat Jan  1 02:53:37 2022
 -- Host        : AW13R3 running 64-bit major release  (build 9200)
 -- Command     : write_vhdl -force -mode synth_stub
 --               v:/srcs/sources/bd/zxnexys/ip/zxnexys_mig_7series_0_0/zxnexys_mig_7series_0_0_stub.vhdl

diff --git a/srcs/sources/bd/zxnexys/ip/zxnexys_pmod_esp32_0_0/sim/zxnexys_pmod_esp32_0_0.v b/srcs/sources/bd/zxnexys/ip/zxnexys_pmod_esp32_0_0/sim/zxnexys_pmod_esp32_0_0.v
@@ -1,4 +1,4 @@
-// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
 // 
 // This file contains confidential and proprietary information
 // of Xilinx, Inc. and is protected under U.S. and

diff --git a/srcs/sources/bd/zxnexys/ip/zxnexys_pmod_esp32_0_0/synth/zxnexys_pmod_esp32_0_0.v b/srcs/sources/bd/zxnexys/ip/zxnexys_pmod_esp32_0_0/synth/zxnexys_pmod_esp32_0_0.v
@@ -1,4 +1,4 @@
-// (c) Copyright 1995-2021 Xilinx, Inc. All rights reserved.
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
 // 
 // This file contains confidential and proprietary information
 // of Xilinx, Inc. and is protected under U.S. and

diff --git a/srcs/sources/bd/zxnexys/ip/zxnexys_pmod_esp32_0_0/zxnexys_pmod_esp32_0_0.dcp b/srcs/sources/bd/zxnexys/ip/zxnexys_pmod_esp32_0_0/zxnexys_pmod_esp32_0_0.dcp
diff --git a/srcs/sources/bd/zxnexys/ip/zxnexys_pmod_esp32_0_0/zxnexys_pmod_esp32_0_0.xml b/srcs/sources/bd/zxnexys/ip/zxnexys_pmod_esp32_0_0/zxnexys_pmod_esp32_0_0.xml
@@ -315,7 +315,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Dec 31 22:35:26 UTC 2021</spirit:value>
+            <spirit:value>Sat Jan 01 02:45:46 UTC 2022</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>outputProductCRC</spirit:name>
@@ -346,7 +346,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Dec 31 22:35:26 UTC 2021</spirit:value>
+            <spirit:value>Sat Jan 01 02:45:46 UTC 2022</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>outputProductCRC</spirit:name>
@@ -365,7 +365,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Dec 31 22:35:26 UTC 2021</spirit:value>
+            <spirit:value>Sat Jan 01 02:45:46 UTC 2022</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>outputProductCRC</spirit:name>
@@ -385,7 +385,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Dec 31 22:35:26 UTC 2021</spirit:value>
+            <spirit:value>Sat Jan 01 02:45:46 UTC 2022</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>outputProductCRC</spirit:name>
@@ -403,7 +403,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>GENtimestamp</spirit:name>
-            <spirit:value>Fri Dec 31 22:38:58 UTC 2021</spirit:value>
+            <spirit:value>Sat Jan 01 02:49:14 UTC 2022</spirit:value>
           </spirit:parameter>
           <spirit:parameter>
             <spirit:name>outputProductCRC</spirit:name>