Fixing/updating makefiles for new xilinx clock test projects

marzoul · Aug 11, 2016 · eb1a393 · eb1a393
1 parent e97054d
commit eb1a393
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Showing 4 changed files with 4 additions and 4 deletions.
diff --git a/fpga/xilinx/vc709/Makefile b/fpga/xilinx/vc709/Makefile
@@ -40,7 +40,7 @@
 # Author:              Dustin Richmond (@darichmond)
 #-----------------------------------------------------------------------
 BOARD:=vc709
-BOARD_PROJECTS:=VC709_Gen1x8If64 VC709_Gen2x8If128 VC709_Gen3x4If128
+BOARD_PROJECTS:=VC709_Gen1x8If64 VC709_Gen2x8If128 VC709_Gen3x4If128 VC709_Gen1x8If64_CLK VC709_Gen2x8If128_CLK
 BOARD_TYPE:=ultrascale
 VENDOR:=xilinx
 include ../vendor.mk
diff --git a/fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/Makefile b/fpga/xilinx/vc709/VC709_Gen1x8If64_CLK/Makefile
@@ -59,4 +59,4 @@ endif
 include $(RIFFA_HDL_PATH)/riffa.mk
 include $(BOARD_PATH)/board.mk
 
-PROJECT_IP+=ip/PCIeGen1x8If64.xci
+PROJECT_IP+=ip/PCIeGen1x8If64.xci ip/clk_250MIn_2/clk_250MIn_2.xci ip/clk_250MIn_1/clk_250MIn_1.xci
diff --git a/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/Makefile b/fpga/xilinx/vc709/VC709_Gen2x8If128_CLK/Makefile
@@ -59,4 +59,4 @@ endif
 include $(RIFFA_HDL_PATH)/riffa.mk
 include $(BOARD_PATH)/board.mk
 
-PROJECT_IP+=ip/PCIeGen2x8If128.xci
+PROJECT_IP+=ip/PCIeGen2x8If128.xci ip/clk_250MIn_2/clk_250MIn_2.xci ip/clk_250MIn_1/clk_250MIn_1.xci
diff --git a/fpga/xilinx/vc709/board.mk b/fpga/xilinx/vc709/board.mk
@@ -78,7 +78,7 @@ all $(TYPE) $(VENDOR) $(BOARD):$(PROJECT)
 clean:
 	echo "reset_run impl_1; reset_run synth_1;" | vivado -mode tcl prj/$(PROJECT).xpr
 	rm -rf *.log *.jou *~ .Xil 
-	rm -rf ip/doc ip/sim ip/source ip/synth ip/*.dcp ip/*.v ip/*.xml ip/*.vhdl ip/*.veo ip/*~
+	rm -rf ip/doc ip/sim ip/source ip/synth ip/*.dcp ip/*.v ip/*.xml ip/*.vhdl ip/*.veo ip/*~ ip/*.txt ip/clk_250MIn_2 ip/clk_250MIn_1
 	rm -rf prj/*.hw prj/*.runs prj/*.cache prj/*~
 
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