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Finishing reset logic and testing/implementing across a wide swath of…
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… boards.

Changes are mostly in the RX logic, where RST_IN was still used, though some new
logic (reset_extender) was added to riffa.v. Updated projects for: VC709, VC707,
ZC706 (partial), NetFPGA, ADM-7V3, ML605 (Still not working), AC701 (Untested)
and KC705 (Untested)
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Dustin Richmond committed Aug 12, 2015
1 parent 9d7543a commit c420b76
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Showing 58 changed files with 667 additions and 320 deletions.
Binary file modified fpga/altera/de2i/DE2Gen1x1If64/bit/DE2Gen1x1If64.sof
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1 change: 1 addition & 0 deletions fpga/altera/de2i/DE2Gen1x1If64/prj/DE2Gen1x1If64.qsf
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Expand Up @@ -160,6 +160,7 @@ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF

set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/reset_extender.v
set_global_assignment -name VERILOG_FILE ../../riffa_wrapper_de2i.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_ultrascale.v
set_global_assignment -name VERILOG_FILE ../../../../riffa_hdl/txr_engine_classic.v
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83 changes: 83 additions & 0 deletions fpga/riffa_hdl/reset_extender.v
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@@ -0,0 +1,83 @@
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
module reset_extender
#(parameter C_RST_COUNT = 10)
(input CLK,
input RST_IN,
output RST_OUT,
output PENDING_RST);

localparam C_CLOG2_RST_COUNT = clog2s(C_RST_COUNT);
localparam C_CEIL2_RST_COUNT = 1 << C_CLOG2_RST_COUNT;
localparam C_RST_SHIFTREG_DEPTH = 4;

wire [C_CLOG2_RST_COUNT:0] wRstCount;
wire [C_RST_SHIFTREG_DEPTH:0] wRstShiftReg;

assign PENDING_RST = RST_IN | (wRstShiftReg != 0);
assign RST_OUT = wRstShiftReg[C_RST_SHIFTREG_DEPTH];

counter
#(// Parameters
.C_MAX_VALUE (C_CEIL2_RST_COUNT),
.C_SAT_VALUE (C_CEIL2_RST_COUNT),
.C_RST_VALUE (C_CEIL2_RST_COUNT - C_RST_COUNT)
/*AUTOINSTPARAM*/)
rst_counter
(// Outputs
.VALUE (wRstCount),
// Inputs
.ENABLE (1'b1),
.RST_IN (RST_IN),
/*AUTOINST*/
// Inputs
.CLK (CLK));

shiftreg
#(// Parameters
.C_DEPTH (C_RST_SHIFTREG_DEPTH),
.C_WIDTH (1),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
rst_shiftreg
(// Outputs
.RD_DATA (wRstShiftReg),
// Inputs
.RST_IN (0),
.WR_DATA (~wRstCount[C_CLOG2_RST_COUNT]),
/*AUTOINST*/
// Inputs
.CLK (CLK));
endmodule
46 changes: 29 additions & 17 deletions fpga/riffa_hdl/riffa.v
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Expand Up @@ -276,7 +276,6 @@ module riffa
wire wTxEngRdReqSent;
wire wRxEngRdComplete;

wire wRstLogic;
wire [31:0] wCPciDataWidth;
reg [31:0] wCFpgaId;

Expand All @@ -285,8 +284,7 @@ module riffa

genvar i;

assign RST_OUT = wRstLogic;
assign wRstLogic = wCoreSettingsReady;

assign wRxEngRdComplete = RXC_DATA_END_FLAG & RXC_DATA_VALID &
(RXC_META_LENGTH >= RXC_META_BYTES_REMAINING[`SIG_BYTECNT_W-1:2]);// TODO: Retime (if possible)

Expand All @@ -302,8 +300,8 @@ module riffa
assign TXC_DATA_START_OFFSET = wTxcDataStartOffset;
assign TXC_DATA_END_FLAG = wTxcDataEndFlag;
assign TXC_DATA_END_OFFSET = wTxcDataEndOffset;
assign TXC_DATA_VALID = wTxcDataValid & ~wRstLogic & DONE_TXC_RST;
assign wTxcDataReady = TXC_DATA_READY & ~wRstLogic & DONE_TXC_RST;
assign TXC_DATA_VALID = wTxcDataValid & ~wPendingRst & DONE_TXC_RST;
assign wTxcDataReady = TXC_DATA_READY & ~wPendingRst & DONE_TXC_RST;

assign TXC_META_FDWBE = wTxcMetaFdwbe;
assign TXC_META_LDWBE = wTxcMetaLdwbe;
Expand All @@ -316,8 +314,8 @@ module riffa
assign TXC_META_TC = wTxcMetaTc;
assign TXC_META_ATTR = wTxcMetaAttr;
assign TXC_META_EP = wTxcMetaEp;
assign TXC_META_VALID = wTxcMetaValid & ~wRstLogic & DONE_TXC_RST;
assign wTxcMetaReady = TXC_META_READY & ~wRstLogic & DONE_TXC_RST;
assign TXC_META_VALID = wTxcMetaValid & ~wPendingRst & DONE_TXC_RST;
assign wTxcMetaReady = TXC_META_READY & ~wPendingRst & DONE_TXC_RST;

/* Workaround for a bug reported by the NetFPGA group, where the parameter
C_PCI_DATA_WIDTH cannot be directly assigned to a wire. */
Expand Down Expand Up @@ -390,10 +388,10 @@ module riffa
_wTxcMetaAttr, _wTxcMetaEp}),
.WR_DATA_VALID (_wTxcMetaValid),
.RD_DATA_READY (wTxcMetaReady),
.RST_IN (RST_BUS),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
.CLK (CLK));

pipeline
#(// Parameters
Expand All @@ -415,18 +413,32 @@ module riffa
_wTxcDataEndOffset}),
.WR_DATA_VALID (_wTxcDataValid),
.RD_DATA_READY (wTxcDataReady),
.RST_IN (RST_BUS),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
.CLK (CLK));

reset_extender
#(.C_RST_COUNT (8)
/*AUTOINSTPARAM*/)
reset_extender_inst
(// Outputs
.PENDING_RST (wPendingRst),
// Inputs
.RST_IN (RST_BUS | wCoreSettingsReady),
/*AUTOINST*/
// Outputs
.RST_OUT (RST_OUT),
// Inputs
.CLK (CLK));

reorder_queue
#(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH),
.C_NUM_CHNL(C_NUM_CHNL),
.C_MAX_READ_REQ_BYTES(C_MAX_READ_REQ_BYTES),
.C_TAG_WIDTH(C_TAG_WIDTH))
reorderQueue
(.RST (wRstLogic),
(.RST (RST_OUT),
.VALID (RXC_DATA_VALID),
.DATA_START_FLAG (RXC_DATA_START_FLAG),
.DATA_START_OFFSET (RXC_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
Expand Down Expand Up @@ -515,7 +527,7 @@ module riffa
.CHNL_TX_DONELEN (wChnlTxDoneLen),
.CHNL_RX_DONELEN (wChnlRxDoneLen),
.INTR_VECTOR (wIntrVector),
.RST_IN (wRstLogic),
.RST_IN (RST_OUT),
.TXC_DATA_READY (_wTxcDataReady),
.TXC_META_READY (_wTxcMetaReady),
/*AUTOINST*/
Expand Down Expand Up @@ -545,7 +557,7 @@ module riffa
// Inputs
.RX_ENG_RD_DONE (wRxEngRdComplete),
.TX_ENG_RD_REQ_SENT (wTxEngRdReqSent),
.RST (wRstLogic),
.RST (RST_OUT),
/*AUTOINST*/
// Inputs
.CLK (CLK),
Expand All @@ -558,7 +570,7 @@ module riffa
#(.C_NUM_CHNL (C_NUM_CHNL))
intr
(// Inputs
.RST (wRstLogic),
.RST (RST_OUT),
.RX_SG_BUF_RECVD (wChnlSgRxBufRecvd),
.RX_TXN_DONE (wChnlRxDone),
.TX_TXN (wChnlTxRequest),
Expand Down Expand Up @@ -597,7 +609,7 @@ module riffa
.INT_TAG_VALID (wInternalTagValid),
.TX_ENG_RD_REQ_SENT (wTxEngRdReqSent),
// Inputs
.RST_IN (wRstLogic),
.RST_IN (RST_OUT),
.WR_REQ (wTxEngWrReq[C_NUM_CHNL-1:0]),
.WR_ADDR (wTxEngWrAddr[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
.WR_LEN (wTxEngWrLen[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
Expand Down Expand Up @@ -644,7 +656,7 @@ module riffa
)
channel
(
.RST(wRstLogic),
.RST(RST_OUT),
.CLK(CLK),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),
Expand Down
4 changes: 2 additions & 2 deletions fpga/riffa_hdl/rx_engine_classic.v
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Expand Up @@ -195,10 +195,10 @@ module rx_engine_classic
.RD_DATA (wRxSrDataValid),
// Inputs
.WR_DATA (RX_TLP_VALID),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
.CLK (CLK));


// End Flag Shift Register. Data valid is deasserted based on the
Expand Down
19 changes: 13 additions & 6 deletions fpga/riffa_hdl/rxc_engine_128.v
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Expand Up @@ -127,6 +127,9 @@ module rxc_engine_128

reg rStraddledSOP;
reg rStraddledSOPSplit;
reg rRST;

assign DONE_RXC_RST = ~rRST;

// ----- Header Register -----
assign __wRxcHdrSOP = RX_SR_SOP[C_RX_INPUT_STAGES] & ~__wRxcStartOffset[1];
Expand Down Expand Up @@ -176,13 +179,17 @@ module rxc_engine_128
// header is not contiguous. (Not sure if this is ever possible, but
// better safe than sorry assert Straddled SOP Split. See Virtex 6 PCIe
// errata.)
if(__wRxcHdrSOP | RST_IN) begin
if(__wRxcHdrSOP) begin
rStraddledSOPSplit <=0;
end else begin
rStraddledSOPSplit <= (rStraddledSOP | rStraddledSOPSplit) & ~RX_SR_VALID[C_RX_INPUT_STAGES];
end

end

always @(posedge CLK) begin
rRST <= RST_BUS | RST_LOGIC;
end

mux
#(
Expand Down Expand Up @@ -215,7 +222,7 @@ module rxc_engine_128
// Inputs
.WR_DATA ({__wRxcHdr[C_STRADDLE_W-1:0], __wRxcHdrValid}),
.WR_EN (__wRxcHdrSOP | rStraddledSOP),
.RST_IN (RST_IN), // TODO: Remove
.RST_IN (0), // TODO: Remove
/*AUTOINST*/
// Inputs
.CLK (CLK));
Expand All @@ -233,7 +240,7 @@ module rxc_engine_128
// Inputs
.WR_DATA (__wRxcHdr[`TLP_MAXHDR_W-1:C_STRADDLE_W]),
.WR_EN (__wRxcHdrSOP | rStraddledSOP | rStraddledSOPSplit), // Non straddled start, Straddled, or straddled split
.RST_IN (RST_IN), // TODO: Remove
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
Expand All @@ -251,7 +258,7 @@ module rxc_engine_128
// Inputs
.WR_DATA ({rStraddledSOP,__wRxcHdrSOP}),
.WR_EN (1),
.RST_IN (RST_IN), // TODO: Remove
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
Expand Down Expand Up @@ -290,7 +297,7 @@ module rxc_engine_128
wRxcHdrSCP, wRxcHdrMCP,
wRxcHdrEndMask, wRxcHdrStartMask}),
// Inputs
.RST_IN (RST_IN),
.RST_IN (rRST),
.WR_DATA ({_wRxcHdrValid,
_wRxcHdrSCP, _wRxcHdrMCP,
_wRxcHdrEndMask, _wRxcHdrStartMask}), // Need to invert the start mask
Expand Down Expand Up @@ -339,7 +346,7 @@ module rxc_engine_128
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
.RST_IN (rRST));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../common")
Expand Down
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