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Finished wiring reset logic in the Engine Layer (untested)
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Expanded DONE_RST into four signals, for each of the four engine interfaces. In
the ultrascale engines, wired up all of the RST and DONE_RST signals. Quickly tested the logic in a power-on-reset like situation, no guarantees on graceful in-transmission resets. Classic engines will have to wait.
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Dustin Richmond committed Jul 16, 2015
1 parent 5ee3747 commit ad90d61
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Showing 16 changed files with 292 additions and 204 deletions.
20 changes: 13 additions & 7 deletions fpga/riffa_hdl/engine_layer.v
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Original file line number Diff line number Diff line change
Expand Up @@ -55,7 +55,10 @@ module engine_layer
// Interface: Resets
input RST_BUS, // Replacement for generic RST_IN
input RST_LOGIC, // Addition for RIFFA_RST
output DONE_RST,
output DONE_TXC_RST,
output DONE_TXR_RST,
output DONE_RXR_RST,
output DONE_RXC_RST,

// Interface: Configuration
input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
Expand Down Expand Up @@ -228,7 +231,8 @@ module engine_layer
rx_engine_classic_inst
(/*AUTOINST*/
// Outputs
.DONE_RST (DONE_RST),
.DONE_RXR_RST (DONE_RXR_RST),
.DONE_RXC_RST (DONE_RXC_RST),
.RX_TLP_READY (RX_TLP_READY),
.RXC_DATA (RXC_DATA[C_PCI_DATA_WIDTH-1:0]),
.RXC_DATA_VALID (RXC_DATA_VALID),
Expand Down Expand Up @@ -287,7 +291,8 @@ module engine_layer
tx_engine_classic_inst
(/*AUTOINST*/
// Outputs
.DONE_RST (DONE_RST),
.DONE_TXC_RST (DONE_TXC_RST),
.DONE_TXR_RST (DONE_TXR_RST),
.TX_TLP (TX_TLP[C_PCI_DATA_WIDTH-1:0]),
.TX_TLP_VALID (TX_TLP_VALID),
.TX_TLP_START_FLAG (TX_TLP_START_FLAG),
Expand Down Expand Up @@ -339,8 +344,7 @@ module engine_layer
.TXR_META_TC (TXR_META_TC[`SIG_TC_W-1:0]),
.TXR_META_ATTR (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
.TXR_META_EP (TXR_META_EP),
.RST_IN (RST_IN));
.TXR_META_EP (TXR_META_EP));

end else begin

Expand All @@ -358,7 +362,8 @@ module engine_layer
rx_engine_ultrascale_inst
(/*AUTOINST*/
// Outputs
.DONE_RST (DONE_RST),
.DONE_RXR_RST (DONE_RXR_RST),
.DONE_RXC_RST (DONE_RXC_RST),
.M_AXIS_CQ_TREADY (M_AXIS_CQ_TREADY),
.M_AXIS_RC_TREADY (M_AXIS_RC_TREADY),
.RXC_DATA (RXC_DATA[C_PCI_DATA_WIDTH-1:0]),
Expand Down Expand Up @@ -420,7 +425,8 @@ module engine_layer
tx_engine_ultrascale_inst
(/*AUTOINST*/
// Outputs
.DONE_RST (DONE_RST),
.DONE_TXC_RST (DONE_TXC_RST),
.DONE_TXR_RST (DONE_TXR_RST),
.S_AXIS_CC_TVALID (S_AXIS_CC_TVALID),
.S_AXIS_CC_TLAST (S_AXIS_CC_TLAST),
.S_AXIS_CC_TDATA (S_AXIS_CC_TDATA[C_PCI_DATA_WIDTH-1:0]),
Expand Down
11 changes: 6 additions & 5 deletions fpga/riffa_hdl/rx_engine_classic.v
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Original file line number Diff line number Diff line change
Expand Up @@ -55,7 +55,8 @@ module rx_engine_classic
// Interface: Resets
input RST_BUS, // Replacement for generic RST_IN
input RST_LOGIC, // Addition for RIFFA_RST
output DONE_RST,
output DONE_RXR_RST,
output DONE_RXC_RST,

// Interface: RX Classic
input [C_PCI_DATA_WIDTH-1:0] RX_TLP,
Expand Down Expand Up @@ -276,7 +277,7 @@ module rx_engine_classic
.RXR_DATA (_RXR_DATA[C_PCI_DATA_WIDTH-1:0]),
/*AUTOINST*/
// Outputs
.DONE_RST (DONE_RST),
.DONE_RXR_RST (DONE_RXR_RST),
.RXR_DATA_VALID (RXR_DATA_VALID),
.RXR_DATA_WORD_ENABLE (RXR_DATA_WORD_ENABLE[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_START_FLAG (RXR_DATA_START_FLAG),
Expand Down Expand Up @@ -324,7 +325,7 @@ module rx_engine_classic
.RXC_DATA (_RXC_DATA[C_PCI_DATA_WIDTH-1:0]),
/*AUTOINST*/
// Outputs
.DONE_RST (DONE_RST),
.DONE_RXC_RST (DONE_RXC_RST),
.RXC_DATA_VALID (RXC_DATA_VALID),
.RXC_DATA_WORD_ENABLE (RXC_DATA_WORD_ENABLE[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_START_FLAG (RXC_DATA_START_FLAG),
Expand Down Expand Up @@ -370,7 +371,7 @@ module rx_engine_classic
.RXR_DATA (_RXR_DATA[C_PCI_DATA_WIDTH-1:0]),
/*AUTOINST*/
// Outputs
.DONE_RST (DONE_RST),
.DONE_RXR_RST (DONE_RXR_RST),
.RXR_DATA_VALID (RXR_DATA_VALID),
.RXR_DATA_WORD_ENABLE (RXR_DATA_WORD_ENABLE[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_START_FLAG (RXR_DATA_START_FLAG),
Expand Down Expand Up @@ -418,7 +419,7 @@ module rx_engine_classic
.RXC_DATA (_RXC_DATA[C_PCI_DATA_WIDTH-1:0]),
/*AUTOINST*/
// Outputs
.DONE_RST (DONE_RST),
.DONE_RXC_RST (DONE_RXC_RST),
.RXC_DATA_VALID (RXC_DATA_VALID),
.RXC_DATA_WORD_ENABLE (RXC_DATA_WORD_ENABLE[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_START_FLAG (RXC_DATA_START_FLAG),
Expand Down
7 changes: 4 additions & 3 deletions fpga/riffa_hdl/rx_engine_ultrascale.v
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Original file line number Diff line number Diff line change
Expand Up @@ -53,7 +53,8 @@ module rx_engine_ultrascale
// Interface: Resets
input RST_BUS, // Replacement for generic RST_IN
input RST_LOGIC, // Addition for RIFFA_RST
output DONE_RST,
output DONE_RXR_RST,
output DONE_RXC_RST,

// Interface: CQ
input M_AXIS_CQ_TVALID,
Expand Down Expand Up @@ -122,7 +123,7 @@ module rx_engine_ultrascale
rxc_engine_inst
(/*AUTOINST*/
// Outputs
.DONE_RST (DONE_RST),
.DONE_RXC_RST (DONE_RXC_RST),
.M_AXIS_RC_TREADY (M_AXIS_RC_TREADY),
.RXC_DATA (RXC_DATA[C_PCI_DATA_WIDTH-1:0]),
.RXC_DATA_VALID (RXC_DATA_VALID),
Expand Down Expand Up @@ -158,7 +159,7 @@ module rx_engine_ultrascale
rxr_engine_inst
(/*AUTOINST*/
// Outputs
.DONE_RST (DONE_RST),
.DONE_RXR_RST (DONE_RXR_RST),
.M_AXIS_CQ_TREADY (M_AXIS_CQ_TREADY),
.RXR_DATA (RXR_DATA[C_PCI_DATA_WIDTH-1:0]),
.RXR_DATA_VALID (RXR_DATA_VALID),
Expand Down
2 changes: 1 addition & 1 deletion fpga/riffa_hdl/rxc_engine_128.v
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Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@ module rxc_engine_128
// Interface: Resets
input RST_BUS, // Replacement for generic RST_IN
input RST_LOGIC, // Addition for RIFFA_RST
output DONE_RST,
output DONE_RXC_RST,

// Interface: RX Classic
input [C_PCI_DATA_WIDTH-1:0] RX_TLP,
Expand Down
5 changes: 2 additions & 3 deletions fpga/riffa_hdl/rxc_engine_classic.v
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Original file line number Diff line number Diff line change
Expand Up @@ -54,7 +54,7 @@ module rxc_engine_classic
// Interface: Resets
input RST_BUS, // Replacement for generic RST_IN
input RST_LOGIC, // Addition for RIFFA_RST
output DONE_RST,
output DONE_RXC_RST,

// Interface: RX Classic
input [C_PCI_DATA_WIDTH-1:0] RX_TLP,
Expand Down Expand Up @@ -89,8 +89,7 @@ module rxc_engine_classic
input [C_RX_PIPELINE_DEPTH:0] RX_SR_EOP,
input [(C_RX_PIPELINE_DEPTH+1)*`SIG_OFFSET_W-1:0] RX_SR_END_OFFSET,
input [C_RX_PIPELINE_DEPTH:0] RX_SR_SOP,
input [C_RX_PIPELINE_DEPTH:0] RX_SR_VALID
);
input [C_RX_PIPELINE_DEPTH:0] RX_SR_VALID);


/*AUTOWIRE*/
Expand Down
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