Mega-commit (which I usually like to avoid, but this one didn't reall…

…y come cleanly)

The majority of this work can be summarized as: Makefiles have been added to
generate all of the boards, boards for each vendor, board, and projects for each
board.

To make things cleaner I renamed a few of the Xilinx projects, and may rename
the latera projects for consistency.

I removed the de5_qsys directory, and moved all projects into the de5 directory,
but those projects have a Q between DE5 and the PCIe specifications, ie
DE5QGen... (haven't updated the documentation)

Added c4dev board (untested)

Apologies to those of you who recently switched onto the DEVEL branch.

fpga/Makefile

@@ -0,0 +1,60 @@
+# ----------------------------------------------------------------------
+# Copyright (c) 2015, The Regents of the University of California All
+# rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+# 
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+# 
+#     * Redistributions in binary form must reproduce the above
+#       copyright notice, this list of conditions and the following
+#       disclaimer in the documentation and/or other materials provided
+#       with the distribution.
+# 
+#     * Neither the name of The Regents of the University of California
+#       nor the names of its contributors may be used to endorse or
+#       promote products derived from this software without specific
+#       prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
+# UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+# TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+# USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+# DAMAGE.
+# ----------------------------------------------------------------------
+
+#include common.mk
+
+MKPATH:=$(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))
+RIFFA_PATH:=$(MKPATH)/riffa_hdl
+VENDORS:= xilinx altera
+SUBDIRS = $(VENDORS)
+
+
+all: $(VENDORS)
+
+$(VENDORS)::
+	$(MAKE) -C $@ $(MAKECMDGOALS) RIFFA_PATH=$(RIFFA_PATH)
+
+.PHONY:clean $(SUBDIRS)
+clean: $(VENDORS)
+	rm -rf *~
+
+
+
+
+
+
+
+
+

fpga/altera/Makefile

@@ -0,0 +1,16 @@
+VENDOR:=altera
+CLASSIC:=de5 de4 de2i c4dev
+CURRENT_PATH := $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))
+RIFFA_PATH=$(CURRENT_PATH)/../riffa_hdl
+
+all: $(VENDOR)
+
+classic:$(CLASSIC)
+
+$(VENDOR): $(CLASSIC)
+$(CLASSIC)::
+	$(MAKE) -C $@ $(MAKECMDGOALS) RIFFA_PATH=$(RIFFA_PATH)
+
+.PHONY:clean $(SUBDIRS)
+clean: $(VENDOR)
+	rm -rf *~ .qsys_edit

fpga/altera/c4dev/C4DevGen1x4If64/Makefile

@@ -0,0 +1,23 @@
+# This make file expects the following variables to be set:
+# RIFFA_PATH -- Path to the riffa_hdl directory in the corresponding RIFFA directory.
+# BOARD_PATH -- Path to the $(BOARD) directory, the board this project corresponds to
+# BOARD_HDL -- A list of an board-specific HDL files not in the riffa_hdl directory
+
+WIDTH=64
+TYPE=classic
+CURRENT_PATH := $(notdir $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST))))))
+PROJECT=$(shell basename $(CURRENT_PATH))
+
+ifndef RIFFA_PATH
+	RIFFA_PATH:=../../../riffa_hdl
+endif
+ifndef BOARD_PATH
+	BOARD_PATH:=..
+endif
+ifndef JOBS
+	JOBS=1
+endif
+include $(RIFFA_PATH)/riffa.mk
+include $(BOARD_PATH)/board.mk
+
+PROJECT_IP+=ip/ALTGXPCIeGen1x4.qip ip/ALTPLL50I50O125O250O.qip ip/PCIeGen1x4If64.qip

fpga/altera/c4dev/C4DevGen1x4If64/constr/C4DevGen1x4If64.sdc

@@ -0,0 +1,23 @@
+# Oscillator Clocks
+create_clock -name CLK1_50 -period 20 [get_ports {CLK1_50}]
+create_clock -name CLK2_50 -period 20 [get_ports {CLK2_50}]
+create_clock -name CLK3_50 -period 20 [get_ports {CLK3_50}]
+
+# Refclk (100 MHz differential input)
+create_clock -period "100 MHz" -name {refclk} [get_ports {PCIE_REFCLK}]
+
+# 50 MHZ PLL Clock
+create_generated_clock -name clk50 -source [get_ports {CLK1_50}] [get_nets {*|altpll_component|auto_generated|wire_pll1_clk[0]}]
+
+# 125 MHZ PLL Clock
+create_generated_clock -name clk125 -multiply_by 5 -divide_by 2 -source [get_ports {CLK1_50}] [get_nets {*|altpll_component|auto_generated|wire_pll1_clk[1]}]
+
+# 250 MHZ PLL Clock
+create_generated_clock -name clk250 -multiply_by 5 -source [get_ports {CLK1_50}] [get_nets {*|altpll_component|auto_generated|wire_pll1_clk[2]}]
+
+derive_pll_clocks 
+derive_clock_uncertainty
+
+# Imported from IP Compiler user guide
+set_clock_groups -exclusive -group [get_clocks { refclk*clkout }] -group [get_clocks { *div0*coreclkout}]
+set_clock_groups -exclusive -group [get_clocks { *central_clk_div0* }] -group [get_clocks { *_hssi_pcie_hip* }] -group [get_clocks { *central_clk_div1* }]