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Initial setup for zynq 045
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marzoul committed Jul 29, 2024
1 parent 5ec92c7 commit f8cbce4
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2 changes: 1 addition & 1 deletion Makefile
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Expand Up @@ -188,7 +188,7 @@ $(foreach DB,$(DATABASES),$(eval $(call database,$(DB))))
# --------------------------------------

ARTIX_PARTS=artix7_50t artix7_200t
ZYNQ_PARTS=zynq7010
ZYNQ_PARTS=zynq7010 zynq7045
KINTEX_PARTS=kintex7_160t
SPARTAN_PARTS=

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4 changes: 4 additions & 0 deletions settings/zynq7/devices.yaml
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@@ -1,4 +1,8 @@
# device to fabric mapping
"xc7z045":
fabric: "xc7z045"
"xc7z035":
fabric: "xc7z045"
"xc7z020":
fabric: "xc7z020"
"xc7z010":
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37 changes: 37 additions & 0 deletions settings/zynq7045.sh
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# Copyright (C) 2017-2020 The Project X-Ray Authors.
#
# Use of this source code is governed by a ISC-style
# license that can be found in the LICENSE file or at
# https://opensource.org/licenses/ISC
#
# SPDX-License-Identifier: ISC
export XRAY_DATABASE="zynq7"
export XRAY_PART="xc7z045ffg900-1"
export XRAY_ROI_FRAMES="0x00000000:0xffffffff"

# All CLB's in part, all BRAM's in part, all DSP's in part.
export XRAY_ROI_TILEGRID=\
"SLICE_X0Y0:SLICE_X171Y349" \
"RAMB18_X0Y0:RAMB18_X8Y139" \
"RAMB36_X0Y0:RAMB36_X8Y69" \
"DSP48_X0Y0:DSP48_X6Y139"

export XRAY_EXCLUDE_ROI_TILEGRID=""

# This is used by fuzzers/005-tilegrid/generate_full.py
# (special handling for frame addresses of certain IOIs -- see the script for details).
# This needs to be changed for any new device!
# If you have a FASM mismatch or unknown bits in IOIs, CHECK THIS FIRST.
export XRAY_IOI3_TILES="LIOI3_X0Y9"

# Note : Actually unknown how to find this for a new part
export XRAY_PS7_INT="INT_L_X18Y300"

source $(dirname ${BASH_SOURCE[0]})/../utils/environment.sh

env=$(python3 ${XRAY_UTILS_DIR}/create_environment.py)
ENV_RET=$?
if [[ $ENV_RET != 0 ]] ; then
return $ENV_RET
fi
eval $env

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