Document blocks in tabular formatting

In tabular formatting, an empty line indicates a block boundary that
restarts the "table". Document that.

(This was implicitly done in the past and discussed in #48 as intended
behavior.)

VerilogCodingStyle.md

@@ -528,6 +528,8 @@ that the identical parts are directly above one another. This alignment makes it
 easy to see which characters are the same and which characters are different
 between lines.
 
+Each block of code, separated by an empty line, is treated as separate "table".
+
 Use spaces, not tabs.
 
 For example:
@@ -538,16 +540,23 @@ logic [7:0]  my_interface_data;
 logic [15:0] my_interface_address;
 logic        my_interface_enable;
 
+logic       another_signal;
+logic [7:0] something_else;
+```
+
 :+1:
 ```systemverilog
 mod u_mod (
   .clk_i,
   .rst_ni,
-  .sig_i (my_signal_in),
-  .sig2_i(my_signal_out),
+  .sig_i          (my_signal_in),
+  .sig2_i         (my_signal_out),
+  // comment with no blank line maintains the block
+  .in_same_block_i(my_signal_in),
+  .sig3_i         (something),
 
   .in_another_block_i(my_signal_in),
-  .sig3_i            (something)
+  .sig4_i            (something)
 );
 ```