Various Fixes #25
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Various Fixes #25
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Cosim needs to make direct use of this to check if certain memory accesses would be allowable under PMP.
This check does not make sense for our cosimulation environment (the spike debug module is not in use) and leads to false failures when randomly generated programs want to access the spike debug memory address range.
When Ibex is executing an instruction it is possible for MIP to change whilst that instruction is stalled in the ID/EX stage. This results in the MIP observed by a CSR instruction differing from the MIP that decides whether or not that instruction may be interrupted which leads to model mis-matches. This adds a new MIP 'pre_val' which is the MIP value used to determine whether or not an interrupt is taken. The existing value is the one observed by CSR instructions. Employing this mechanism avoids the mis-matches described above.
marnovandermaas
approved these changes
Jul 2, 2024
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These accompany fixes in the Ibex repository: lowRISC/ibex#2183