Update Python Debug Modules and fix Virtual Timer clock issue #61
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Ensure there could not be more than one handler assigned to each logger, to avoid duplication of messages. Signed-off-by: Emmanuel Blot <[email protected]>
Signed-off-by: Emmanuel Blot <[email protected]>
Signed-off-by: Emmanuel Blot <[email protected]>
- use a cache to track transitions for TMS sequences - use a cache to update current state from new transitions Signed-off-by: Emmanuel Blot <[email protected]>
- reduce log evaluation for low level comm traces - use local bytearray to build TCP packet - use local variables for JTAG signal management Signed-off-by: Emmanuel Blot <[email protected]>
Signed-off-by: Emmanuel Blot <[email protected]>
Signed-off-by: Emmanuel Blot <[email protected]>
Output is similar to `hexdump -C` Signed-off-by: Emmanuel Blot <[email protected]>
Signed-off-by: Emmanuel Blot <[email protected]>
Should only report the first line of the module documentation Signed-off-by: Emmanuel Blot <[email protected]>
Basic features, limited to RV32 and 32-bit operations: - read/write DM registers - read/write CSR and registers or RISC-V core - read/write memory - load and execute ELF file Signed-off-by: Emmanuel Blot <[email protected]>
Signed-off-by: Emmanuel Blot <[email protected]>
Signed-off-by: Emmanuel Blot <[email protected]>
….misc Signed-off-by: Emmanuel Blot <[email protected]>
Signed-off-by: Emmanuel Blot <[email protected]>
Signed-off-by: Emmanuel Blot <[email protected]>
…er DM Signed-off-by: Emmanuel Blot <[email protected]>
Signed-off-by: Emmanuel Blot <[email protected]>
Signed-off-by: Emmanuel Blot <[email protected]>
Signed-off-by: Emmanuel Blot <[email protected]>
Signed-off-by: Emmanuel Blot <[email protected]>
VIRTUAL timer is paced with icount setting; VIRTUAL_RT is not. This means that as the higher icount, the less instruction executed in a given time slot, VIRTUAL_RT makes HW timer relatively much faster from the guest standpoint. Signed-off-by: Emmanuel Blot <[email protected]>
Signed-off-by: Emmanuel Blot <[email protected]>
… bug - CSR value is not required when no CSR check is requested - remove useless update of TDI signal - implement System Bus "fast mode" transfer Signed-off-by: Emmanuel Blot <[email protected]>
- remove useless setter/getter for TMS and TDI - remove useless TMS update, already performed by state selection Signed-off-by: Emmanuel Blot <[email protected]>
* TAP IR length * DMI base address Signed-off-by: Emmanuel Blot <[email protected]>
Signed-off-by: Emmanuel Blot <[email protected]>
loiclefort
approved these changes
Apr 16, 2024
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