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Add JTAG Debug Module support for Ibex core #58

Merged
merged 44 commits into from
Mar 19, 2024
Merged

Add JTAG Debug Module support for Ibex core #58

merged 44 commits into from
Mar 19, 2024

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@rivos-eblot
[ot] scripts/jtag: fix invalid .pylintrc format
ad5e109 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] scripts/jtag: add unit tests and fix bits.py
61a740f 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] scripts/opentitan: tap.py a tiny bitbang TAP controller simulator.
a0d425f 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] jtag: jtag_bitbang.c: add a trace for JTAG TDO read
9c6208c 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] target/riscv: fix a regression introduced in upstream d1c1114
caaf7e1 
do_trigger_action was introduced by commit d1c1114 and takes a trigger index
as parameter.
riscv_cpu_debug_excp_handler is also changed to call do_trigger_action but is
passing an action enum value (DBG_ACTION_BP) into the trigger index parameter.

Change do_trigger_action parameter from a trigger index to a trigger_action_t
to satisfy all callers.

Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] hw/opentitan: remove set_next_dm definition
3c56a2a 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] gdbstub: bypass GDB server if server is not enabled
48843e2 
cpu_handle_guest_debug() calls this function and we want to call 
guest debugging from alternative debug implementation(s) to GDB.

Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] target/riscv: debug: add __func__ to all qemu_log messages.
280b92e 
This matches the common syntax for qemu_log calls

Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] target/riscv: define dscratch CSR count
f09f87a 
RISC-V DM supports up to 2 dscratch registers; many implementations use 2.

Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] target/riscv: increase max trigger CSRs to 4
0f675ee 
This is the default configuration with OpenTitan project.

Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] target/riscv: add debug CSRs (dcsr, dpc, dscratch)
e05c904 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] disas: export debug register names
042f252 
This enables accessing CSR register names for trace/log purposes.

Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] target/riscv: restore debug_mode to previous state
e1b9d3a 
Accessing a CSR in debug mode should not reset debug mode. This should be
a transient state to allow accessing CSR register in debug mode.

Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] target/riscv: stop execution on singlestep
12dc526 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] target/riscv: trigger CSRs are not debug CSRs
6aadb19 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] target/riscv: add debug CSRs access functions
f4fec28 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] target/riscv: disable instruction counting on DCSR/STOPCOUNT
1cf073c 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] target/riscv: add a marker to signal debug module is available
d96c824 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] target/riscv: add DRET instruction support
4ca6571 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] target/riscv: store cause for entering debug mode
fceed3c 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] target/riscv: ignore WFI when debug mode is active
c43e760 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] hw/core: add two new optional debug handlers to CPU
550105b 
* cpu_handle_guest_debug may delegate debug exception handling to debug_request
* cpu_exec_loop may delegate single stepping handling to debug_enable_singlestep

Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] target/riscv: implement debug_request function for RISC-V
619f2cb 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] target/riscv: implement debug_enable_singlestep function for RISC-V
3484807 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] target/riscv: ignore priv. modification in debug mode w/o MPRV e…
bd0b31e 
…nabled

Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] target/riscv: do not serve interrupt while in debug mode or sstep
69c1351 
Note that DCSR STEPIE is not yet supported.

Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] target/riscv: do not resume debug exception processing if handled
2de983b 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] target/riscv: trans_privileged: handle WFI as NOP when single st…
98e67db 
…epping

Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] target/riscv: add support for actionable debugger action
2636ddb 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] target/riscv: handle breakpoint exception in debugger mode
bcd3394 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] target/riscv: add debug exception handling in debugger mode
3737e25 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] system: delegate guest_debug to debug_request function if any
deb4c03 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] accel/tcg: delegate single stepping feature to CPU implementation
246d10d 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] target/riscv: jump to debug halt vector debug cause is known
7c10afd 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] target/riscv: add Trigger CSRs management for remote debugger
5507f7b 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] scripts/opentitan: pyot: fix negative test filter management
f2de269 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
Revert "[ot] .gitlab-ci.d: fix pyot test filter for EarlGrey"
8cfe568 
This reverts commit b1c5948, now that
pyot.py has been fixed.

Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] hw/riscv: create RISC-V Debug Module
37becd6 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] hw/misc: create PULP RISC-V debug module device
445a818 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] hw/misc: pulp_rv_dm: add OpenTitan comportable Alert Test support
14444f4 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] scripts/opentitan: update config files for clang-format and clan…
59c9ae4 
…g-tidy

Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] hw/riscv: ibexdemo: add JTAG/DMI/DM support
2459ca7 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] hw/riscv: ot_earlgrey: add JTAG/DMI/DM support
42148d3 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot
[ot] hw/riscv: ot_darjeeling: add DM support
62b0c19 
Signed-off-by: Emmanuel Blot <[email protected]>
@rivos-eblot rivos-eblot requested a review from loiclefort March 19, 2024 17:18
loiclefort
loiclefort approved these changes Mar 19, 2024
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LGTM (already reviewed and tested at Rivos)

@rivos-eblot rivos-eblot merged commit b46d6c2 into lowRISC:ot-darjeeling-8.2.0 Mar 19, 2024
5 checks passed
@rivos-eblot rivos-eblot deleted the dev/ebl/jtag_sync branch March 19, 2024 17:31
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@loiclefort loiclefort loiclefort approved these changes

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@rivos-eblot @loiclefort