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[ot] scripts/opentitan: dtm.py add support for custom DTMCS and DMI r…
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…egister.

This is required for the IbexDemo project

Signed-off-by: Emmanuel Blot <[email protected]>
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rivos-eblot committed Dec 5, 2024
1 parent 2087a41 commit 470fcba
Showing 1 changed file with 17 additions and 5 deletions.
22 changes: 17 additions & 5 deletions scripts/opentitan/dtm.py
Original file line number Diff line number Diff line change
Expand Up @@ -27,6 +27,7 @@

from ot.dm import DebugModule
from ot.dtm import DebugTransportModule
from ot.dtm.dtm import DMI, DTMCS
from ot.util.elf import ElfBlob
from ot.util.log import configure_loggers
from ot.util.misc import HexInt, dump_buffer
Expand All @@ -37,7 +38,7 @@
from pyftdi import __version__ as PyFtdiVersion
from pyftdi.jtag import JtagFtdiController
except ImportError as _exc:
_FTDI_ERR = str(_exc).split(':')[-1]
_FTDI_ERR = str(_exc).split(':', 1)[-1]
JtagFtdiController = None


Expand All @@ -48,9 +49,8 @@
"""Default DMI address of the DM."""


def idcode(engine: JtagEngine, ir_length: int) -> None:
def idcode(engine: JtagEngine, code: int, ir_length: int) -> int:
"""Retrieve ID code."""
code = JtagBitbangController.INSTRUCTIONS['idcode']
engine.write_ir(BitSequence(code, ir_length))
engine.read_dr(32)
engine.go_idle()
Expand All @@ -62,7 +62,7 @@ def main():
"""Entry point."""
debug = True
default_socket = f'tcp:localhost:{JtagBitbangController.DEFAULT_PORT}'
default_port = JtagBitbangController.DEFAULT_PORT
default_idcode = JtagBitbangController.INSTRUCTIONS['idcode']
try:
args: Optional[Namespace] = None
argparser = ArgumentParser(
Expand All @@ -78,6 +78,14 @@ def main():
default=DEFAULT_IR_LENGTH,
help=f'bit length of the IR register '
f'(default: {DEFAULT_IR_LENGTH})')
dmi.add_argument('--idcode', type=int, default=default_idcode,
help=f'define the ID code (default: {default_idcode})')
dmi.add_argument('--dtmcs', type=HexInt.parse,
help=f'define an alternative DTMCS register '
f'(default: 0x{DTMCS.ADDRESS:x})')
dmi.add_argument('--dmi', type=HexInt.parse,
help=f'define an alternative DMI register '
f'(default: 0x{DMI.ADDRESS:x})')
dmi.add_argument('-b', '--base', type=HexInt.parse,
default=DEFAULT_DMI_ADDRESS,
help=f'define DMI base address '
Expand Down Expand Up @@ -157,11 +165,15 @@ def main():
eng = JtagEngine(ctrl)
ctrl.tap_reset(trst)
ir_length = args.ir_length
if args.dtmcs:
DTMCS.ADDRESS = args.dtmcs
if args.dmi:
DMI.ADDRESS = args.dmi
dtm = DebugTransportModule(eng, ir_length)
rvdm = None
try:
if args.info:
code = idcode(eng, ir_length)
code = idcode(eng, args.idcode, ir_length)
print(f'IDCODE: 0x{code:x}')
version = dtm['dtmcs'].dmi_version
abits = dtm['dtmcs'].abits
Expand Down

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