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This commit adds the following FI tests: - ibex.fi.address_translation - ibex.fi.address_translation_config - ibex.fi.char.csr_write - ibex.fi.char.csr_read The device code is located in lowRISC/opentitan#22269 Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org>
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39 changes: 39 additions & 0 deletions
39
fault_injection/configs/pen.global_fi.ibex.address_translation.cw310.yaml
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target: | ||
target_type: cw310 | ||
fpga_bitstream: "../objs/lowrisc_systems_chip_earlgrey_cw310_0.1.bit" | ||
force_program_bitstream: False | ||
fw_bin: "../objs/sca_ujson_fpga_cw310.bin" | ||
output_len_bytes: 16 | ||
target_clk_mult: 0.24 | ||
target_freq: 24000000 | ||
baudrate: 115200 | ||
protocol: "ujson" | ||
port: "/dev/ttyACM4" | ||
fisetup: | ||
fi_gear: "husky" | ||
fi_type: "voltage_glitch" | ||
parameter_generation: "random" | ||
# Voltage glitch width in cycles. | ||
glitch_width_min: 5 | ||
glitch_width_max: 150 | ||
glitch_width_step: 3 | ||
# Range for trigger delay in cycles. | ||
trigger_delay_min: 0 | ||
trigger_delay_max: 500 | ||
trigger_step: 10 | ||
# Number of iterations for the parameter sweep. | ||
num_iterations: 100 | ||
fiproject: | ||
# Project database type and memory threshold. | ||
project_db: "ot_fi_project" | ||
project_mem_threshold: 10000 | ||
# Store FI plot. | ||
show_plot: True | ||
num_plots: 10 | ||
plot_x_axis: "trigger_delay" | ||
plot_x_axis_legend: "[cycles]" | ||
plot_y_axis: "glitch_width" | ||
plot_y_axis_legend: "[cycles]" | ||
test: | ||
which_test: "ibex_address_translation" | ||
expected_result: '{"result":0,"err_status":0}' |
39 changes: 39 additions & 0 deletions
39
fault_injection/configs/pen.global_fi.ibex.address_translation_config.cw310.yaml
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target: | ||
target_type: cw310 | ||
fpga_bitstream: "../objs/lowrisc_systems_chip_earlgrey_cw310_0.1.bit" | ||
force_program_bitstream: False | ||
fw_bin: "../objs/sca_ujson_fpga_cw310.bin" | ||
output_len_bytes: 16 | ||
target_clk_mult: 0.24 | ||
target_freq: 24000000 | ||
baudrate: 115200 | ||
protocol: "ujson" | ||
port: "/dev/ttyACM4" | ||
fisetup: | ||
fi_gear: "husky" | ||
fi_type: "voltage_glitch" | ||
parameter_generation: "random" | ||
# Voltage glitch width in cycles. | ||
glitch_width_min: 5 | ||
glitch_width_max: 150 | ||
glitch_width_step: 3 | ||
# Range for trigger delay in cycles. | ||
trigger_delay_min: 0 | ||
trigger_delay_max: 500 | ||
trigger_step: 10 | ||
# Number of iterations for the parameter sweep. | ||
num_iterations: 100 | ||
fiproject: | ||
# Project database type and memory threshold. | ||
project_db: "ot_fi_project" | ||
project_mem_threshold: 10000 | ||
# Store FI plot. | ||
show_plot: True | ||
num_plots: 10 | ||
plot_x_axis: "trigger_delay" | ||
plot_x_axis_legend: "[cycles]" | ||
plot_y_axis: "glitch_width" | ||
plot_y_axis_legend: "[cycles]" | ||
test: | ||
which_test: "ibex_address_translation_config" | ||
expected_result: '{"result":0,"err_status":0}' |
39 changes: 39 additions & 0 deletions
39
fault_injection/configs/pen.global_fi.ibex.char.csr_read.cw310.yaml
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,39 @@ | ||
target: | ||
target_type: cw310 | ||
fpga_bitstream: "../objs/lowrisc_systems_chip_earlgrey_cw310_0.1.bit" | ||
force_program_bitstream: False | ||
fw_bin: "../objs/sca_ujson_fpga_cw310.bin" | ||
output_len_bytes: 16 | ||
target_clk_mult: 0.24 | ||
target_freq: 24000000 | ||
baudrate: 115200 | ||
protocol: "ujson" | ||
port: "/dev/ttyACM4" | ||
fisetup: | ||
fi_gear: "husky" | ||
fi_type: "voltage_glitch" | ||
parameter_generation: "random" | ||
# Voltage glitch width in cycles. | ||
glitch_width_min: 5 | ||
glitch_width_max: 150 | ||
glitch_width_step: 3 | ||
# Range for trigger delay in cycles. | ||
trigger_delay_min: 0 | ||
trigger_delay_max: 500 | ||
trigger_step: 10 | ||
# Number of iterations for the parameter sweep. | ||
num_iterations: 100 | ||
fiproject: | ||
# Project database type and memory threshold. | ||
project_db: "ot_fi_project" | ||
project_mem_threshold: 10000 | ||
# Store FI plot. | ||
show_plot: True | ||
num_plots: 10 | ||
plot_x_axis: "trigger_delay" | ||
plot_x_axis_legend: "[cycles]" | ||
plot_y_axis: "glitch_width" | ||
plot_y_axis_legend: "[cycles]" | ||
test: | ||
which_test: "ibex_char_csr_read" | ||
expected_result: '{"result":0,"err_status":0}' |
39 changes: 39 additions & 0 deletions
39
fault_injection/configs/pen.global_fi.ibex.char.csr_write.cw310.yaml
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@@ -0,0 +1,39 @@ | ||
target: | ||
target_type: cw310 | ||
fpga_bitstream: "../objs/lowrisc_systems_chip_earlgrey_cw310_0.1.bit" | ||
force_program_bitstream: False | ||
fw_bin: "../objs/sca_ujson_fpga_cw310.bin" | ||
output_len_bytes: 16 | ||
target_clk_mult: 0.24 | ||
target_freq: 24000000 | ||
baudrate: 115200 | ||
protocol: "ujson" | ||
port: "/dev/ttyACM4" | ||
fisetup: | ||
fi_gear: "husky" | ||
fi_type: "voltage_glitch" | ||
parameter_generation: "random" | ||
# Voltage glitch width in cycles. | ||
glitch_width_min: 5 | ||
glitch_width_max: 150 | ||
glitch_width_step: 3 | ||
# Range for trigger delay in cycles. | ||
trigger_delay_min: 0 | ||
trigger_delay_max: 500 | ||
trigger_step: 10 | ||
# Number of iterations for the parameter sweep. | ||
num_iterations: 100 | ||
fiproject: | ||
# Project database type and memory threshold. | ||
project_db: "ot_fi_project" | ||
project_mem_threshold: 10000 | ||
# Store FI plot. | ||
show_plot: True | ||
num_plots: 10 | ||
plot_x_axis: "trigger_delay" | ||
plot_x_axis_legend: "[cycles]" | ||
plot_y_axis: "glitch_width" | ||
plot_y_axis_legend: "[cycles]" | ||
test: | ||
which_test: "ibex_char_csr_write" | ||
expected_result: '{"result":0,"err_status":0}' |
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