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[ci] Add test capture
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vrozic committed Sep 25, 2023
1 parent de2ab37 commit 7ffafe5
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2 changes: 1 addition & 1 deletion ci/azure-pipelines.yml
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Expand Up @@ -10,4 +10,4 @@ jobs:
vmImage: ubuntu-latest
steps:
- bash: |
echo Hello, world!
./ci_capture_aes_fvsr.sh
30 changes: 30 additions & 0 deletions ci/ci_capture_aes_cw310.yaml
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device:
fpga_bitstream: ../cw/objs/lowrisc_systems_chip_earlgrey_cw310_0.1.bit
force_program_bitstream: True
fw_bin: ../cw/objs/aes_serial_fpga_cw310.bin
pll_frequency: 100000000
baudrate: 115200
capture:
# Only AES-128 ECB is supported at this moment.
key_len_bytes: 16
plain_text_len_bytes: 16
output_len_bytes: 16
# Samples per trace - We oversample by 20x and AES w/ DOM is doing
# ~56/72 cycles per encryption (AES-128/256).
num_samples: 1200
# Offest in samples - The AES idle signal becomes visible 1 target clock
# cycle later (20 samples) and there are 2 synchronization stages at 100 MHz
# at the top level (4 samples).
offset: -40
# 32-bit seed for SW key masking. Key masks are generated using an LFSR.
# To switch off the masking, 0 must be used as LFSR seed.
lfsr_seed: 0xdeadbeef
batch_prng_seed: 0
scope_gain: 31.5
num_traces: 1000
project_name: ci_projects/opentitan_simple_aes
waverunner_ip: 192.168.1.228
plot_capture:
show: False
num_traces: 100
trace_image_filename: null
8 changes: 8 additions & 0 deletions ci/ci_capture_aes_fvsr.sh
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#!/bin/bash
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0

# Simple script to test AES fvsr-key capture
../cw/capture.py --cfg-file ci_capture_aes_cw310.yaml capture aes-fvsr-key-batch
[ -d "./ci_projects/opentitan_simple_aes_data" ] && echo "Directory ./ci_projects/opentitan_simple_aes_data exists" || echo "Error: Directory ./ci_projects/opentitan_simple_aes_data does not exists."

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