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[fi] Add OTBN command handlers
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This commit adds command handlers for the following tests:
- otbn_key_sideload
- otbn_load_integrity

The device code is located in lowRISC/opentitan#21917. The
binary was created from lowRISC/opentitan@55091e7 with
./bazelisk.sh build //sw/device/tests/crypto/cryptotest/firmware:firmware_fpga_cw310_test_rom

Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org>
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nasahlpa committed Mar 21, 2024
1 parent 7c38c87 commit 679d99f
Showing 5 changed files with 120 additions and 7 deletions.
2 changes: 1 addition & 1 deletion ci/cfg/ci_otbn_fi_vcc_dummy_cw310.yaml
Original file line number Diff line number Diff line change
@@ -8,7 +8,7 @@ target:
target_freq: 24000000
baudrate: 115200
protocol: "ujson"
port: "/dev/ttyACM1"
port: "/dev/ttyACM_CW310_1"
# Trigger source.
# hw: Precise, hardware-generated trigger - FPGA only.
# sw: Fully software-controlled trigger.
38 changes: 38 additions & 0 deletions fault_injection/configs/pen.global_fi.otbn.key_sideload.cw310.yaml
Original file line number Diff line number Diff line change
@@ -0,0 +1,38 @@
target:
target_type: cw310
fpga_bitstream: "../objs/lowrisc_systems_chip_earlgrey_cw310_0.1.bit"
force_program_bitstream: False
fw_bin: "../objs/sca_ujson_fpga_cw310.bin"
output_len_bytes: 16
target_clk_mult: 0.24
target_freq: 24000000
baudrate: 115200
protocol: "ujson"
port: "/dev/ttyACM1"
fisetup:
fi_gear: "husky"
fi_type: "voltage_glitch"
# Voltage glitch width in cycles.
glitch_width_min: 5
glitch_width_max: 150
glitch_width_step: 3
# Range for trigger delay in cycles.
trigger_delay_min: 0
trigger_delay_max: 500
trigger_step: 10
# Number of iterations for the parameter sweep.
num_iterations: 10000
fiproject:
# Project database type and memory threshold.
project_db: "ot_fi_project"
project_mem_threshold: 10000
# Store FI plot.
show_plot: True
num_plots: 100
plot_x_axis: "trigger_delay"
plot_x_axis_legend: "[cycles]"
plot_y_axis: "glitch_width"
plot_y_axis_legend: "[cycles]"
test:
which_test: "otbn_key_sideload"
expected_result: '{"result":0,"err_status":0}'
Original file line number Diff line number Diff line change
@@ -0,0 +1,38 @@
target:
target_type: cw310
fpga_bitstream: "../objs/lowrisc_systems_chip_earlgrey_cw310_0.1.bit"
force_program_bitstream: False
fw_bin: "../objs/sca_ujson_fpga_cw310.bin"
output_len_bytes: 16
target_clk_mult: 0.24
target_freq: 24000000
baudrate: 115200
protocol: "ujson"
port: "/dev/ttyACM1"
fisetup:
fi_gear: "husky"
fi_type: "voltage_glitch"
# Voltage glitch width in cycles.
glitch_width_min: 5
glitch_width_max: 150
glitch_width_step: 3
# Range for trigger delay in cycles.
trigger_delay_min: 0
trigger_delay_max: 500
trigger_step: 10
# Number of iterations for the parameter sweep.
num_iterations: 10000
fiproject:
# Project database type and memory threshold.
project_db: "ot_fi_project"
project_mem_threshold: 10000
# Store FI plot.
show_plot: True
num_plots: 100
plot_x_axis: "trigger_delay"
plot_x_axis_legend: "[cycles]"
plot_y_axis: "glitch_width"
plot_y_axis_legend: "[cycles]"
test:
which_test: "otbn_load_integrity"
expected_result: '{"result":0,"err_status":0}'
8 changes: 5 additions & 3 deletions fault_injection/fi_otbn.py
Original file line number Diff line number Diff line change
@@ -78,6 +78,8 @@ def fi_parameter_sweep(cfg: dict, target: Target, fi_gear,
project: The project to store the results.
ot_communication: The OpenTitan OTBN FI communication interface.
"""
# Setup key manager if needed by test.
ot_communication.init_keymgr(cfg["test"]["which_test"])
# Configure the trigger.
ot_communication.init_trigger()
# Start the parameter sweep.
@@ -87,15 +89,13 @@ def fi_parameter_sweep(cfg: dict, target: Target, fi_gear,
while remaining_iterations > 0:
# Get fault parameters (e.g., trigger delay, glitch voltage).
fault_parameters = fi_gear.generate_fi_parameters()

# Arm the FI gear.
fi_gear.arm_trigger(fault_parameters)

# Start test on OpenTitan.
ot_communication.start_test(cfg)

# Read response.
response = ot_communication.read_response()
response = ot_communication.read_response(max_tries=20)

# Compare response.
# Check if result is expected result (FI failed), unexpected result
@@ -111,6 +111,8 @@ def fi_parameter_sweep(cfg: dict, target: Target, fi_gear,
ot_communication = target.reset_target(com_reset = True)
# Re-establish UART connection.
ot_communication = OTFIOtbn(target)
# Setup key manager if needed by test.
ot_communication.init_keymgr(cfg["test"]["which_test"])
# Configure the trigger.
ot_communication.init_trigger()
# Reset FIGear if necessary.
41 changes: 38 additions & 3 deletions target/communication/fi_otbn_commands.py
Original file line number Diff line number Diff line change
@@ -54,11 +54,46 @@ def otbn_char_hardware_dmem_op_loop(self) -> None:
time.sleep(0.01)
self.target.write(json.dumps("CharHardwareDmemOpLoop").encode("ascii"))

def init_trigger(self) -> None:
""" Initialize the FI trigger on the chip.
def otbn_key_sideload(self) -> None:
""" Starts the otbn.fi.key_sideload test.
"""
# OtbnFi command.
self._ujson_otbn_fi_cmd()
# KeySideload command.
time.sleep(0.01)
self.target.write(json.dumps("KeySideload").encode("ascii"))

def otbn_load_integrity(self) -> None:
""" Starts the otbn.fi.load_integrity test.
"""
# OtbnFi command.
self._ujson_otbn_fi_cmd()
# LoadIntegrity command.
time.sleep(0.01)
self.target.write(json.dumps("LoadIntegrity").encode("ascii"))

def init_keymgr(self, test: str) -> None:
""" Initialize the key manager on the chip.
Args:
cfg: Config dict containing the selected test.
test: Name of the test. Used to determine if key manager init is
needed.
"""
if "key_sideload" in test:
# OtbnFi command.
self._ujson_otbn_fi_cmd()
# InitTrigger command.
time.sleep(0.01)
self.target.write(json.dumps("InitKeyMgr").encode("ascii"))
# As the init resets the chip, we need to call it again to complete
# the initialization of the key manager.
time.sleep(2)
self._ujson_otbn_fi_cmd()
time.sleep(0.01)
self.target.write(json.dumps("InitKeyMgr").encode("ascii"))
time.sleep(2)

def init_trigger(self) -> None:
""" Initialize the FI trigger on the chip.
"""
# OtbnFi command.
self._ujson_otbn_fi_cmd()

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