[ipgen] Move SPI_HOST to ipgen

BLOCKFILE

@@ -61,7 +61,6 @@ hw/ip/rv_core_ibex/rtl/*
 hw/ip/rv_dm/rtl/*
 hw/ip/rv_timer/rtl/*
 hw/ip/spi_device/rtl/*
-hw/ip/spi_host/rtl/*
 hw/ip/sram_ctrl/rtl/*
 hw/ip/sysrst_ctrl/rtl/*
 hw/ip/tlul/rtl/*
@@ -117,6 +116,7 @@ hw/top_earlgrey/ip_autogen/pinmux/data/pinmux.hjson
 hw/top_earlgrey/ip_autogen/pwrmgr/data/pwrmgr.hjson
 hw/top_earlgrey/ip_autogen/rstmgr/data/rstmgr.hjson
 hw/top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson
+hw/top_earlgrey/ip_autogen/spi_host/data/spi_host.hjson
 
 hw/top_earlgrey/data/top_earlgrey.hjson
 hw/top_earlgrey/data/xbar_main.hjson

SUMMARY.md

@@ -309,15 +309,15 @@
     - [Registers](./hw/ip/spi_device/doc/registers.md)
     - [Device Interface Functions](./sw/device/lib/dif/dif_spi_device.h)
     - [Checklist](./hw/ip/spi_device/doc/checklist.md)
-  - [SPI Host](./hw/ip/spi_host/README.md)
-    - [Theory of Operation](./hw/ip/spi_host/doc/theory_of_operation.md)
-    - [Design Verification](./hw/ip/spi_host/dv/README.md)
-      - [Testplan](./hw/ip/spi_host/data/spi_host_testplan.hjson)
-    - [Programmer's Guide](./hw/ip/spi_host/doc/programmers_guide.md)
-    - [Hardware Interfaces](./hw/ip/spi_host/doc/interfaces.md)
-    - [Registers](./hw/ip/spi_host/doc/registers.md)
+  - [SPI Host](./hw/top_earlgrey/ip_autogen/spi_host/README.md)
+    - [Theory of Operation](./hw/top_earlgrey/ip_autogen/spi_host/doc/theory_of_operation.md)
+    - [Design Verification](./hw/top_earlgrey/ip_autogen/spi_host/dv/README.md)
+      - [Testplan](./hw/top_earlgrey/ip_autogen/spi_host/data/spi_host_testplan.hjson)
+    - [Programmer's Guide](./hw/top_earlgrey/ip_autogen/spi_host/doc/programmers_guide.md)
+    - [Hardware Interfaces](./hw/top_earlgrey/ip_autogen/spi_host/doc/interfaces.md)
+    - [Registers](./hw/top_earlgrey/ip_autogen/spi_host/doc/registers.md)
     - [Device Interface Functions](./sw/device/lib/dif/dif_spi_host.h)
-    - [Checklist](./hw/ip/spi_host/doc/checklist.md)
+    - [Checklist](./hw/top_earlgrey/ip_autogen/spi_host/doc/checklist.md)
   - [SRAM Controller](./hw/ip/sram_ctrl/README.md)
     - [Theory of Operation](./hw/ip/sram_ctrl/doc/theory_of_operation.md)
     - [Design Verification](./hw/ip/sram_ctrl/dv/README.md)

hw/ip/BUILD

@@ -32,7 +32,6 @@ filegroup(
         "//hw/ip/rv_dm:all_files",
         "//hw/ip/rv_timer:all_files",
         "//hw/ip/spi_device:all_files",
-        "//hw/ip/spi_host:all_files",
         "//hw/ip/sram_ctrl:all_files",
         "//hw/ip/sysrst_ctrl:all_files",
         "//hw/ip/tlul:all_files",

hw/ip/README.md

@@ -30,7 +30,6 @@
 | [`rv_timer`]     | Memory-mapped timer unit implementing RISC-V mtime and mtimecmp registers                                                         |
 | [`soc_dbg_ctrl`] | Control module to enable or disable debug access                                                                                  |
 | [`spi_device`]   | Serial peripheral interface supporting different device modes, suitable for bulk-load of data into and out of the chip            |
-| [`spi_host`]     | Serial peripheral interface for host mode, suitable for interfacing external serial NOR flash devices                             |
 | [`sram_ctrl`]    | Interfacing on-chip SRAM blocks with system bus, supports lightweight scrambling, integrity and secure wipe                       |
 | [`sysrst_ctrl`]  | Manages board-level reset sequencing, interfaces reset and power manager                                                          |
 | [`uart`]         | Full duplex serial communication interface, supports bit rates of up to 1 Mbit/s                                                  |
@@ -65,7 +64,6 @@
 [`rv_timer`]: ./rv_timer/README.md
 [`soc_dbg_ctrl`]: ./soc_dbg_ctrl/README.md
 [`spi_device`]: ./spi_device/README.md
-[`spi_host`]: ./spi_host/README.md
 [`sram_ctrl`]: ./sram_ctrl/README.md
 [`sysrst_ctrl`]: ./sysrst_ctrl/README.md
 [`uart`]: ./uart/README.md

hw/ip_templates/BUILD

@@ -12,5 +12,6 @@ filegroup(
         "//hw/ip_templates/pinmux:all_files",
         "//hw/ip_templates/pwrmgr:all_files",
         "//hw/ip_templates/rstmgr:all_files",
+        "//hw/ip_templates/spi_host:all_files",
     ],
 )

hw/ip/spi_host/BUILD → hw/ip_templates/spi_host/BUILD

@@ -6,7 +6,5 @@ package(default_visibility = ["//visibility:public"])
 
 filegroup(
     name = "all_files",
-    srcs = glob(["**"]) + [
-        "//hw/ip/spi_host/data:all_files",
-    ],
+    srcs = glob(["**"]),
 )

hw/ip_templates/spi_host/BUILD.tpl

@@ -0,0 +1,30 @@
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+package(default_visibility = ["//visibility:public"])
+
+load(
+    "//rules:autogen.bzl",
+    "autogen_hjson_c_header",
+    "autogen_hjson_rust_header",
+)
+
+autogen_hjson_c_header(
+    name = "spi_host_c_regs",
+    srcs = [
+        "data/spi_host.hjson",
+    ],
+)
+
+autogen_hjson_rust_header(
+    name = "spi_host_rust_regs",
+    srcs = [
+        "data/spi_host.hjson",
+    ],
+)
+
+filegroup(
+    name = "all_files",
+    srcs = glob(["**"]),
+)

hw/ip/spi_host/README.md → hw/ip_templates/spi_host/README.md

@@ -9,7 +9,7 @@
 # Overview
 
 This document specifies SPI_HOST hardware IP (HWIP) functionality.
-This module conforms to the [Comportable guideline for peripheral functionality.](../../../doc/contributing/hw/comportability/README.md)
+This module conforms to the [Comportable guideline for peripheral functionality.](https://opentitan.org/book/doc/contributing/hw/comportability).
 See that document for integration overview within the broader top-level system.
 
 ## Features
@@ -32,7 +32,7 @@ See that document for integration overview within the broader top-level system.
    - Additional support for "Full-cycle" SPI transactions, wherein data can be read a full SPI Clock cycle after the active edge (as opposed to one half cycle as is typical for SPI interfaces)
 - Single Transfer Rate (STR) only (i.e. data received on multiple lines, but only on one clock edge)
    - *No support* for Dual Transfer Rate (DTR)
-- Pass-through mode for coordination with [SPI_DEVICE IP](../spi_device/README.md)
+- Pass-through mode for coordination with [SPI_DEVICE IP](../../../ip/spi_device/README.md)
 - Automatic control of chip select lines
 - Condensed interrupt footprint: Two lines for two distinct interrupt classes: "error" and "spi_event"
    - Fine-grain interrupt masking supplied by secondary enable registers