Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

[sival] Enable CW340 exec. environment for ECC tests #25537

Merged
merged 2 commits into from
Dec 9, 2024
Merged
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
7 changes: 4 additions & 3 deletions sw/device/tests/BUILD
Original file line number Diff line number Diff line change
Expand Up @@ -2599,14 +2599,14 @@ opentitan_test(
name = "otbn_mem_scramble_test",
srcs = ["otbn_mem_scramble_test.c"],
exec_env = dicts.add(
EARLGREY_TEST_ENVS,
EARLGREY_SILICON_OWNER_ROM_EXT_ENVS,
{
"//hw/top_earlgrey:fpga_cw340_sival": None,
"//hw/top_earlgrey:silicon_creator": None,
"//hw/top_earlgrey:sim_dv": None,
"//hw/top_earlgrey:sim_verilator": None,
},
),
# TODO(#12486) [bazel] targets in sw/device/tests failing on cw310 and verilator when built by bazel
fpga = fpga_params(tags = ["broken"]),
verilator = verilator_params(timeout = "long"),
deps = [
"//hw/top_earlgrey/sw/autogen:top_earlgrey",
Expand Down Expand Up @@ -6603,6 +6603,7 @@ opentitan_test(
name = "sram_ctrl_scrambled_access_test",
srcs = ["sram_ctrl_scrambled_access_test.c"],
exec_env = dicts.add(
EARLGREY_CW340_TEST_ENVS,
EARLGREY_TEST_ENVS,
EARLGREY_SILICON_OWNER_ROM_EXT_ENVS,
),
Expand Down
9 changes: 5 additions & 4 deletions sw/device/tests/sram_ctrl_scrambled_access_test.c
Original file line number Diff line number Diff line change
Expand Up @@ -267,16 +267,17 @@ static void check_sram_data(scramble_test_frame *mem_frame) {

// Decide whether to perform ECC error count checks after memory is scrambled.
//
// This is not done on FPGAs because the interrupt handler that counts them
// does not currently trigger on our FPGA platforms.
// See #20119 for more details.
// This is not done on CW305/CW310 FPGAs because interrupts for ECC errors are
// only triggered when the SecureIbex parameter is enabled. This parameter is
// disabled for these boards due to resource constraints. On CW340 and the
// other targets, this parameter is enabled.
bool check_ecc_errors = false;
switch (kDeviceType) {
case kDeviceFpgaCw305:
case kDeviceFpgaCw310:
case kDeviceFpgaCw340:
check_ecc_errors = false;
break;
case kDeviceFpgaCw340:
case kDeviceSilicon:
case kDeviceSimDV:
case kDeviceSimVerilator:
Expand Down
Loading