[prim] Remove primgen and replace with virtual cores

.github/workflows/bitstream.yml

@@ -82,11 +82,21 @@ jobs:
         if: steps.strategy.outputs.bitstreamStrategy != 'cached'
         run: |
           . util/build_consts.sh
+
+          vlnv_path=lowrisc_systems_chip_${{ inputs.top_name }}_${{ inputs.design_suffix }}_0.1
+          design_name=chip_${{ inputs.top_name }}_${{ inputs.design_suffix }}
+
           echo "Synthesis log"
-          cat $OBJ_DIR/hw/top_${{ inputs.top_name }}/build.fpga_${{ inputs.design_suffix }}/synth-vivado/lowrisc_systems_chip_${{ inputs.top_name }}_${{ inputs.design_suffix }}_0.1.runs/synth_1/runme.log || true
+          cat $OBJ_DIR/hw/top_${{ inputs.top_name }}/${design_name}/build.fpga_${{ inputs.design_suffix }}/${vlnv_path}/synth-vivado/${vlnv_path}.runs/synth_1/runme.log || true
 
           echo "Implementation log"
-          cat $OBJ_DIR/hw/top_${{ inputs.top_name }}/build.fpga_${{ inputs.design_suffix }}/synth-vivado/lowrisc_systems_chip_${{ inputs.top_name }}_${{ inputs.design_suffix }}_0.1.runs/impl_1/runme.log || true
+          cat $OBJ_DIR/hw/top_${{ inputs.top_name }}/${design_name}/build.fpga_${{ inputs.design_suffix }}/${vlnv_path}/synth-vivado/${vlnv_path}.runs/impl_1/runme.log || true
+
+          echo "Utilization report"
+          cat $OBJ_DIR/hw/top_${{ inputs.top_name }}/${design_name}/build.fpga_${{ inputs.design_suffix }}/${vlnv_path}/synth-vivado/${vlnv_path}.runs/impl_1/${design_name}_utilization_placed.rpt || true
+
+          echo "Timing summary report"
+          cat $OBJ_DIR/hw/top_${{ inputs.top_name }}/${design_name}/build.fpga_${{ inputs.design_suffix }}/${vlnv_path}/synth-vivado/${vlnv_path}.runs/impl_1/${design_name}_timing_summary_routed.rpt || true
 
       - name: Upload step outputs
         uses: actions/upload-artifact@v4

ci/scripts/build-bitstream-vivado.sh

@@ -102,8 +102,11 @@ fusesoc --verbose --cores-root=. \
   --BootRomInitFile="$BOOTROM_VMEM" \
   $OTP_ARG
 
-BITSTREAM_FNAME="lowrisc_systems_chip_${FLAVOUR}_${TARGET}_0.1.bit"
-BITSTREAM_PATH="$OBJ_DIR/hw/synth-vivado/$BITSTREAM_FNAME"
+
+VLNV_PATH="lowrisc_systems_chip_${FLAVOUR}_${TARGET}_0.1"
+
+BITSTREAM_FNAME="${VLNV_PATH}.bit"
+BITSTREAM_PATH="$OBJ_DIR/hw/${VLNV_PATH}/synth-vivado/${BITSTREAM_FNAME}"
 cp "$BITSTREAM_PATH" "$TOPLEVEL_BIN_DIR"
 
 cp "$OBJ_DIR/hw/synth-vivado/memories.mmi" "$TOPLEVEL_BIN_DIR"

ci/scripts/build-chip-verilator.sh

@@ -20,13 +20,15 @@ case "$tl" in
     earlgrey)
         fileset=fileset_top
         fusesoc_core=lowrisc:dv:chip_verilator_sim
+        vlnv_path=lowrisc_dv_chip_verilator_sim_0.1
         vname=Vchip_sim_tb
         verilator_options="--threads 4"
         make_options="-j 4"
         ;;
     englishbreakfast)
         fileset=fileset_topgen
         fusesoc_core=lowrisc:systems:chip_englishbreakfast_verilator
+        vlnv_path=lowrisc_systems_chip_englishbreakfast_verilator_0.1
         vname=Vchip_englishbreakfast_verilator
         # Englishbreakfast on CI runs on a 2-core CPU
         verilator_options="--threads 2"
@@ -55,5 +57,5 @@ fusesoc --cores-root=. \
   --verilator_options="${verilator_options}" \
   --make_options="${make_options}"
 
-cp "$OBJ_DIR/hw/sim-verilator/${vname}" \
+cp "$OBJ_DIR/hw/${vlnv_path}/sim-verilator/${vname}" \
    "$BIN_DIR/hw/top_${tl}/Vchip_${tl}_verilator"

doc/contributing/fpga/ref_manual_fpga.md

@@ -29,7 +29,7 @@ For example, see the `//hw/bitstream:rom` target defined in [hw/bitstream/BUILD]
     There are two prerequisites in order for this flow to work:
 
     * The boot ROM during the build process must be correctly inferred by the tool.
-      * See [prim_rom](https://github.com/lowRISC/opentitan/blob/master/hw/ip/prim_generic/rtl/prim_generic_rom.sv) and [vivado_hook_opt_design_post.tcl](https://github.com/lowRISC/opentitan/blob/master/hw/top_earlgrey/util/vivado_hook_opt_design_post.tcl).
+      * See [prim_rom](https://github.com/lowRISC/opentitan/blob/master/hw/ip/prim_generic/rtl/prim_rom.sv) and [vivado_hook_opt_design_post.tcl](https://github.com/lowRISC/opentitan/blob/master/hw/top_earlgrey/util/vivado_hook_opt_design_post.tcl).
     * The MMI file outlining the physical boot ROM placement and mapping to FPGA block RAM primitives needs to be generated by the tool.
       * See [vivado_hook_write_bitstream_pre.tcl](https://github.com/lowRISC/opentitan/blob/master/hw/top_earlgrey/util/vivado_hook_write_bitstream_pre.tcl).
 

hw/BUILD

@@ -43,7 +43,7 @@ fusesoc_build(
     data = ["//hw/ip/otbn:all_files"],
     make_options = ":make_options",
     output_groups = {
-        "binary": ["sim-verilator/Vchip_sim_tb"],
+        "binary": ["lowrisc_dv_chip_verilator_sim_0.1/sim-verilator/Vchip_sim_tb"],
     },
     systems = ["lowrisc:dv:chip_verilator_sim"],
     tags = [

hw/bitstream/vivado/BUILD

@@ -13,12 +13,12 @@ load("//rules:bitstreams.bzl", "bitstream_manifest_fragment")
 package(default_visibility = ["//visibility:public"])
 
 # The readmem directives in the fusesoc-ized build tree will be in the subdir
-# ${build_root}/src/lowrisc_prim_util_memload_0/rtl/prim_util_memload.svh,
+# ${build_root}/${core}/${target}-${tool}/src/lowrisc_prim_util_memload_0/rtl/prim_util_memload.svh,
 # and ${build_root} will be a subdirectory called `build.fpga_cw310` inside of
 # bazel-out/k8-{configname}/bin/hw/bitstream/vivado.
 # Therefore, the relative path between prim_util_memload.svh and the project-root
 # relative $(location ...) resolved labels is up 10 subdirectories.
-_PREFIX = "../../../../../../../../../.."
+_PREFIX = "../../../../../../../../../../.."
 
 _CW310_TESTROM = "//sw/device/lib/testing/test_rom:test_rom_fpga_cw310_scr_vmem"
 
@@ -32,6 +32,8 @@ _CW340_TESTROM_PATH = _CW310_TESTROM_PATH
 
 _OTP_RMA_PATH = "{}/$(location {})".format(_PREFIX, _OTP_RMA)
 
+_FPGA_PATH_TMPL = "lowrisc_systems_{}_0.1/synth-vivado/{}"
+
 # Note: all of the targets are tagged with "manual" to prevent them from being
 # matched by bazel wildcards like "//...".  In order to build the bitstream,
 # you need to ask for it directly or by dependency via another rule, such as
@@ -51,9 +53,9 @@ fusesoc_build(
         "--OtpCtrlMemInitFile=" + _OTP_RMA_PATH,
     ],
     output_groups = {
-        "bitstream": ["synth-vivado/lowrisc_systems_chip_earlgrey_cw310_0.1.bit"],
-        "mmi": ["synth-vivado/memories.mmi"],
-        "logs": ["synth-vivado/lowrisc_systems_chip_earlgrey_cw310_0.1.runs/"],
+        "bitstream": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw310", "lowrisc_systems_chip_earlgrey_cw310_0.1.bit")],
+        "mmi": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw310", "memories.mmi")],
+        "logs": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw310", "lowrisc_systems_chip_earlgrey_cw310_0.1.runs/")],
     },
     systems = ["lowrisc:systems:chip_earlgrey_cw310"],
     tags = ["manual"],
@@ -92,9 +94,9 @@ fusesoc_build(
         "--OtpCtrlMemInitFile=" + _OTP_RMA_PATH,
     ],
     output_groups = {
-        "bitstream": ["synth-vivado/lowrisc_systems_chip_earlgrey_cw310_hyperdebug_0.1.bit"],
-        "mmi": ["synth-vivado/memories.mmi"],
-        "logs": ["synth-vivado/lowrisc_systems_chip_earlgrey_cw310_hyperdebug_0.1.runs/"],
+        "bitstream": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw310_hyperdebug", "lowrisc_systems_chip_earlgrey_cw310_hyperdebug_0.1.bit")],
+        "mmi": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw310_hyperdebug", "memories.mmi")],
+        "logs": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw310_hyperdebug", "lowrisc_systems_chip_earlgrey_cw310_hyperdebug_0.1.runs/")],
     },
     systems = ["lowrisc:systems:chip_earlgrey_cw310_hyperdebug"],
     tags = ["manual"],
@@ -133,9 +135,9 @@ fusesoc_build(
         "--OtpCtrlMemInitFile=" + _OTP_RMA_PATH,
     ],
     output_groups = {
-        "bitstream": ["synth-vivado/lowrisc_systems_chip_earlgrey_cw340_0.1.bit"],
-        "mmi": ["synth-vivado/memories.mmi"],
-        "logs": ["synth-vivado/lowrisc_systems_chip_earlgrey_cw340_0.1.runs/"],
+        "bitstream": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw340", "lowrisc_systems_chip_earlgrey_cw340_0.1.bit")],
+        "mmi": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw340", "memories.mmi")],
+        "logs": [_FPGA_PATH_TMPL.format("chip_earlgrey_cw340", "lowrisc_systems_chip_earlgrey_cw340_0.1.runs/")],
     },
     systems = ["lowrisc:systems:chip_earlgrey_cw340"],
     tags = ["manual"],

hw/dv/dpi/dpi_sim_cfg.hjson

@@ -10,12 +10,12 @@
   build_modes: [
     {
       name: vcs_dpi_build_opts
-      build_opts: ["-CFLAGS -I{build_dir}/src/{dpi_common_dir}", "-lutil"]
+      build_opts: ["-CFLAGS -I{build_dir}/fusesoc-work/src/{dpi_common_dir}", "-lutil"]
     }
 
     {
       name: xcelium_dpi_build_opts
-      build_opts: ["-I{build_dir}/src/{dpi_common_dir}", "-lutil"]
+      build_opts: ["-I{build_dir}/fusesoc-work/src/{dpi_common_dir}", "-lutil"]
     }
   ]
 }

hw/dv/sv/sec_cm/prim_sparse_fsm_flop_if.sv

@@ -23,7 +23,7 @@ interface prim_sparse_fsm_flop_if #(
   string msg_id = $sformatf("%m");
 
   string path = dv_utils_pkg::get_parent_hier($sformatf("%m"));
-  string signal_forced = $sformatf("%s.u_state_flop.q_o", path);
+  string signal_forced = $sformatf("%s.state_o", path);
 
   // This signal only has to be forced if the associated parameter
   // CustomForceName in prim_sparse_fsm_flop is set to a non-empty string.

hw/dv/sv/tl_agent/dv/tl_agent_sim.core

@@ -8,6 +8,7 @@ filesets:
   files_dv:
     depend:
       - lowrisc:dv:tl_agent_test
+      - lowrisc:prim_generic:all
     files:
       - tb/tb.sv
     file_type: systemVerilogSource

hw/dv/tools/dvsim/fusesoc.hjson

@@ -8,10 +8,10 @@
                        "run",
                        "{sv_flist_gen_flags}",
                        "--target=sim",
-                       "--build-root={build_dir}",
+                       "--work-root={build_dir}/fusesoc-work",
                        "--setup {fusesoc_core}"]
   fusesoc_cores_root_dirs: ["--cores-root {proj_root}"]
-  sv_flist_gen_dir:   "{build_dir}/sim-vcs"
+  sv_flist_gen_dir:   "{build_dir}/fusesoc-work"
   sv_flist:           "{sv_flist_gen_dir}/{fusesoc_core_}.scr"
   sv_flist_gen_flags: ["--flag=fileset_{design_level}"]
 }

hw/dv/tools/dvsim/xcelium.hjson

@@ -46,7 +46,7 @@
                // Ignore warning "Include directory <path> given but not used". This is benign.
                "-nowarn SPDUSD",
                // Needed for including "secded_enc.h".
-               "-I{build_dir}/src/lowrisc_dv_secded_enc_0",
+               "-I{build_dir}/fusesoc-work/src/lowrisc_dv_secded_enc_0",
                // This warning is thrown when a scalar enum variable is assigned to an enum array.
                // Other tools (e.g., FPV) treat such assignments as an error, hence we bump it to
                // an error in simulation so that this can be caught early in CI.

hw/dv/verilator/cpp/scrambled_ecc32_mem_area.cc

@@ -117,10 +117,8 @@ std::vector<uint8_t> ScrambledEcc32MemArea::GetScrambleNonce() const {
 ScrambledEcc32MemArea::ScrambledEcc32MemArea(const std::string &scope,
                                              uint32_t size, uint32_t width_32,
                                              bool repeat_keystream)
-    : Ecc32MemArea(
-          SVScoped::join_sv_scopes(
-              scope, "u_prim_ram_1p_adv.u_mem.gen_generic.u_impl_generic"),
-          size, width_32),
+    : Ecc32MemArea(SVScoped::join_sv_scopes(scope, "u_prim_ram_1p_adv.u_mem"),
+                   size, width_32),
       scr_scope_(scope) {
   addr_width_ = vbits(size);
   repeat_keystream_ = repeat_keystream;

hw/dv/verilator/memutil_dpi_scrambled_opts.hjson

@@ -24,29 +24,29 @@
   build_modes: [
     {
       name: vcs_memutil_dpi_scrambled_build_opts
-      build_opts: ["-CFLAGS -I{build_dir}/src/{memutil_dpi_src_dir}/cpp",
-                   "-CFLAGS -I{build_dir}/src/{memutil_dpi_scrambled_src_dir}/cpp",
-                   "-CFLAGS -I{build_dir}/src/{secded_enc_src_dir}",
-                   "-CFLAGS -I{build_dir}/src/{scramble_model_dir}",
-                   "-CFLAGS -I{build_dir}/src/{prince_ref_src_dir}",
+      build_opts: ["-CFLAGS -I{build_dir}/fusesoc-work/src/{memutil_dpi_src_dir}/cpp",
+                   "-CFLAGS -I{build_dir}/fusesoc-work/src/{memutil_dpi_scrambled_src_dir}/cpp",
+                   "-CFLAGS -I{build_dir}/fusesoc-work/src/{secded_enc_src_dir}",
+                   "-CFLAGS -I{build_dir}/fusesoc-work/src/{scramble_model_dir}",
+                   "-CFLAGS -I{build_dir}/fusesoc-work/src/{prince_ref_src_dir}",
                    "-lelf"]
     }
 
     {
       name: xcelium_memutil_dpi_scrambled_build_opts
-      build_opts: ["-I{build_dir}/src/{memutil_dpi_src_dir}/cpp",
-                   "-I{build_dir}/src/{memutil_dpi_scrambled_src_dir}/cpp",
-                   "-I{build_dir}/src/{prince_ref_src_dir}",
-                   "-I{build_dir}/src/{scramble_model_dir}",
+      build_opts: ["-I{build_dir}/fusesoc-work/src/{memutil_dpi_src_dir}/cpp",
+                   "-I{build_dir}/fusesoc-work/src/{memutil_dpi_scrambled_src_dir}/cpp",
+                   "-I{build_dir}/fusesoc-work/src/{prince_ref_src_dir}",
+                   "-I{build_dir}/fusesoc-work/src/{scramble_model_dir}",
                    "-lelf"]
     }
 
     {
       name: dsim_memutil_dpi_scrambled_build_opts
-      build_opts: ["-c-opts -I{build_dir}/src/{memutil_dpi_src_dir}/cpp",
-                   "-c-opts -I{build_dir}/src/{memutil_dpi_scrambled_src_dir}/cpp",
-                   "-c-opts -I{build_dir}/src/{prince_ref_src_dir}",
-                   "-c-opts -I{build_dir}/src/{scramble_model_dir}",
+      build_opts: ["-c-opts -I{build_dir}/fusesoc-work/src/{memutil_dpi_src_dir}/cpp",
+                   "-c-opts -I{build_dir}/fusesoc-work/src/{memutil_dpi_scrambled_src_dir}/cpp",
+                   "-c-opts -I{build_dir}/fusesoc-work/src/{prince_ref_src_dir}",
+                   "-c-opts -I{build_dir}/fusesoc-work/src/{scramble_model_dir}",
                    "-ld-opts -lelf"]
     }
   ]

hw/ip/adc_ctrl/adc_ctrl.core

@@ -41,6 +41,10 @@ filesets:
       - lowrisc:lint:common
       - lowrisc:lint:comportable
 
+  files_lint:
+    depend:
+      - lowrisc:prim_generic:all
+
 parameters:
   SYNTHESIS:
     datatype: bool
@@ -59,6 +63,8 @@ targets:
   lint:
     <<: *default_target
     default_tool: verilator
+    filesets_append:
+      - files_lint
     parameters:
       - SYNTHESIS=true
     tools:

hw/ip/adc_ctrl/dv/adc_ctrl_sim.core

@@ -14,6 +14,7 @@ filesets:
       - lowrisc:dv:adc_ctrl_test
       - lowrisc:dv:adc_ctrl_sva
       - lowrisc:dv:adc_ctrl_cov
+      - lowrisc:prim_generic:all
     files:
       - tb.sv
     file_type: systemVerilogSource

hw/ip/adc_ctrl/dv/env/adc_ctrl_env.core

@@ -40,6 +40,7 @@ generate:
     parameters:
       name: adc_ctrl
       ip_hjson: ../../data/adc_ctrl.hjson
+    position: prepend
 
 targets:
   default:

hw/ip/aes/aes.core

@@ -79,6 +79,10 @@ filesets:
       - lowrisc:lint:common
       - lowrisc:lint:comportable
 
+  files_lint:
+    depend:
+      - lowrisc:prim_generic:all
+
 parameters:
   SYNTHESIS:
     datatype: bool
@@ -97,6 +101,8 @@ targets:
   lint:
     <<: *default_target
     default_tool: verilator
+    filesets_append:
+      - files_lint
     parameters:
       - SYNTHESIS=true
     tools:

hw/ip/aes/aes_wrap.core

@@ -36,6 +36,10 @@ filesets:
       - lowrisc:lint:common
       - lowrisc:lint:comportable
 
+  files_lint:
+    depend:
+      - lowrisc:prim_generic:all
+
 parameters:
   SYNTHESIS:
     datatype: bool
@@ -54,6 +58,8 @@ targets:
   lint:
     <<: *default_target
     default_tool: verilator
+    filesets_append:
+      - files_lint
     parameters:
       - SYNTHESIS=true
     tools:

hw/ip/aes/dv/aes_sim.core

@@ -15,6 +15,7 @@ filesets:
       - lowrisc:dv:aes_sva
       - lowrisc:dv:aes_err_injection
       - lowrisc:dv:aes_cov
+      - lowrisc:prim_generic:all
     files:
       - tb/tb.sv
     file_type: systemVerilogSource

hw/ip/aes/dv/env/aes_env.core

@@ -52,6 +52,7 @@ generate:
     parameters:
       name: aes
       ip_hjson: ../../data/aes.hjson
+    position: prepend
 
 targets:
   default:

hw/ip/aes/model/aes_model_sim_opts.hjson

@@ -10,12 +10,12 @@
   build_modes: [
     {
       name: vcs_aes_model_build_opts
-      build_opts: ["-CFLAGS -I{build_dir}/src/{aes_model_src_dir}", "-lcrypto"]
+      build_opts: ["-CFLAGS -I{build_dir}/fusesoc-work/src/{aes_model_src_dir}", "-lcrypto"]
     }
 
     {
       name: xcelium_aes_model_build_opts
-      build_opts: ["-I{build_dir}/src/{aes_model_src_dir}", "-lcrypto"]
+      build_opts: ["-I{build_dir}/fusesoc-work/src/{aes_model_src_dir}", "-lcrypto"]
     }
   ]
 }

hw/ip/aon_timer/aon_timer.core

@@ -42,6 +42,10 @@ filesets:
       - lowrisc:lint:common
       - lowrisc:lint:comportable
 
+  files_lint:
+    depend:
+      - lowrisc:prim_generic:all
+
 parameters:
   SYNTHESIS:
     datatype: bool
@@ -59,6 +63,8 @@ targets:
   lint:
     <<: *default_target
     default_tool: verilator
+    filesets_append:
+      - files_lint
     parameters:
       - SYNTHESIS=true
     tools:

hw/ip/aon_timer/dv/aon_timer_sim.core

@@ -13,6 +13,7 @@ filesets:
     depend:
       - lowrisc:dv:aon_timer_test
       - lowrisc:dv:aon_timer_sva
+      - lowrisc:prim_generic:all
     files:
       - tb.sv
     file_type: systemVerilogSource

hw/ip/aon_timer/dv/env/aon_timer_env.core

@@ -31,6 +31,7 @@ generate:
     parameters:
       name: aon_timer
       ip_hjson: ../../data/aon_timer.hjson
+    position: prepend
 
 targets:
   default: