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[hw] OTBN Sync for Integrated #22993

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12cf255
[pre_syn] Include csrng_pkg.sv to re-enable Yosys synthesis
vogelpi Jan 20, 2024
54c0b99
[otbn] Fix interpretation of lc_rma_req signal values
vogelpi Aug 31, 2023
5d6cee7
[otbn] Add missing CM annotation
msfschaffner Feb 12, 2024
8f156e2
[otbn] Detect unexpected partial "secure" wipes
vogelpi May 2, 2024
5023041
[doc] Fix typo & wrong links in OTBN
nasahlpa Feb 22, 2024
fadd044
[doc] otbn registers and interfaces now use CMDGEN
HU90m Aug 13, 2023
375a2e4
[dv,otbn] Add reg dump and a deterministic build to the smoke test.
HU90m Feb 26, 2024
4760cf9
[sw,otbn] Added the `otbn_isa_test`
HU90m Feb 26, 2024
e517238
[otbn,dv] otbn_model_if needs to have ImemSizeByte parameter
GregAC Mar 15, 2024
e0b9a2a
[otbn,dv] Wait longer for model status change after escalation
rswarbrick Jul 17, 2023
196dc7c
[otbn,dv] Wrap some secure wipe assertions in a named block
rswarbrick Aug 10, 2023
e7e0ac7
[otbn,doc] Extract list of ISRs into YAML files
rswarbrick Nov 10, 2023
05fa78c
[otbn,python] Fix incorrectly indented line in insn_yaml.py
rswarbrick Nov 21, 2023
730152f
[otbn,python] Tweak code to avoid some flake8 errors
rswarbrick Nov 21, 2023
d057213
[otbn]: Add ISR support to otbn_as and otbn_objdump
rswarbrick Nov 13, 2023
046ed83
[doc] Fix CSR and WSR tables in OTBN README
sarranz Dec 12, 2023
12979b4
[otbn,dv] Make types slightly cleaner in ext_regs.py
rswarbrick Sep 6, 2023
16d6aa4
[otbn,dv] Add underscores to some internal fields in wsr.py
rswarbrick Sep 6, 2023
469846c
[otbn,dv] Get rid of "_out" field in wsr.py
rswarbrick Sep 6, 2023
43805fc
[otbn,dv] Make update of URND _state field slightly clearer
rswarbrick Sep 6, 2023
7fcd06e
[otbn,dv] Remove bogus abort() for URND in wsr.py
rswarbrick Sep 6, 2023
2ad0682
[otbn,dv] Remove some do-nothing 'return' lines in wsr.py
rswarbrick Sep 6, 2023
6876cb1
[otbn,dv] Simplify types for URND value/next_value in wsr.py
rswarbrick Sep 6, 2023
37f4cc5
[otbn,dv] Be more explicit about not tracking URND changes in wsr.py
rswarbrick Sep 6, 2023
a78b5d8
[dv,otbn] Fix otbn_env.core missing dependency
matutem Sep 30, 2023
f5be812
[otbn,dv] Disable RTL assertions in otbn_zero_state_err_urnd test
rswarbrick Jul 18, 2023
4b779b6
[dv,otbn] Fix raw hierarchical reference in a sequence
matutem Sep 30, 2023
970ed9e
[otbn,dv] Delay "start" signal for OTBN in pre-DV code by a cycle
rswarbrick Aug 14, 2023
139f090
[otbn,dv] Add a "safe" mode to RIG; use it in otbn_ctrl_redun test
rswarbrick Aug 9, 2023
73ac8a0
[otbn,dv] Factor out some UVM spin-wait logic
rswarbrick Jul 13, 2023
53f72d6
[otbn,dv] Correct HDL access in otbn_ctrl_redun_vseq.sv
rswarbrick Aug 8, 2023
b8f899d
[otbn,dv] Strengthen otbn_ctrl_redun_vseq check
rswarbrick Aug 8, 2023
9a61c32
[otbn,dv] Rewrite a line more efficiently in wsr.py
rswarbrick Sep 5, 2023
355829e
[otbn,dv] Make "dirty" flag more selective in otbnsim ext_regs.py
rswarbrick Sep 5, 2023
efd39bc
[otbn,dv] Be more explicit in yields in insn.py
rswarbrick Jul 3, 2023
de261af
[otbn,dv] Wait longer for secure wipe in otbn_intg_err_vseq
rswarbrick Jul 18, 2023
f2848fc
[otbn,dv] Fix trivial Python lint bugs in otbnsim
rswarbrick Jun 19, 2023
9cf84ea
[otbn,dv] Avoid Xcelium lint warning in otbn_trace_if
rswarbrick Jul 13, 2023
43012c9
[otbn,dv] Properly notice mismatches in insn_cnt in otbn_top_sim.sv
rswarbrick Jun 21, 2023
39f91f4
[otbn,dv] Don't apply loop warps in Verilator when no longer running
rswarbrick Jun 28, 2023
09345c9
[otbn,dv] Wait more carefully for secure wipes in vseqs
rswarbrick Jul 13, 2023
fdeae42
[otbn,dv] Explicitly check some calls to uvm_hdl_read
rswarbrick Jul 13, 2023
1d85079
[otbn,dv] Add some missing "protected" keywords to vseqs
rswarbrick Jul 13, 2023
954fbad
[otbn,dv] Wait long enough for RF read in otbn_rf_base_intg_err_vseq
rswarbrick Jul 18, 2023
3ef84c5
[aes, kmac, otbn] Perform final `clean -purge` step in Yosys synthesis
vogelpi Dec 12, 2023
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[otbn,dv] Disable RTL assertions in otbn_zero_state_err_urnd test
The problem is that the design RTL contains assertions like
InitSecWipeNonZeroBaseRegs_A, which assert that each register has been
initialised to a nonzero value during secure wipe. This is reasonable,
but isn't true in this test: that's kind of the point!

Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
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rswarbrick authored and sameo committed May 7, 2024
commit f5be8128601954445a2224b742cd0c621fdd2ca1
Original file line number Diff line number Diff line change
Expand Up @@ -7,6 +7,14 @@ class otbn_zero_state_err_urnd_vseq extends otbn_single_vseq;
`uvm_object_new

task body();
// Disable some assertions in the RTL which assert that the base registers don't get
// secure-wiped to zero. Of course, they do in this test, so we need to disable the assertions.
//
// Note that we can't disable them more specifically because there is at least one assertion for
// each register and you can't use a "for" loop because $assertoff() expects a hierarchical
// identifier for the assertion to control, rather than just an expression.
$assertoff(0, tb.dut);

do_end_addr_check = 0;
fork
begin
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