[pentest] Batch mode for Ibex SCA #22272

nasahlpa · 2024-03-26T18:47:21Z

This commit adds the following new FI and SCA ibex tests:

ibex_sca_tl_write_batch_fvsr
ibex_sca_tl_write_batch_fvsr_fix_address
ibex_sca_tl_write_batch_random
ibex_sca_tl_write_batch_random_fix_address
ibex_sca_tl_write_fvsr
ibex_sca_tl_write_random
ibex_sca_tl_read_batch_fvsr
ibex_sca_tl_read_batch_fvsr_fix_address
ibex_sca_tl_read_batch_random
ibex_sca_tl_read_batch_random_fix_address
ibex_sca_tl_read_fvsr
ibex_sca_tl_read_random
ibex_sca_register_file_write_batch_fvsr
ibex_sca_register_file_write_batch_random
ibex_sca_register_file_write_fvsr
ibex_sca_register_file_write_random
ibex_sca_register_file_read_batch_fvsr
ibex_sca_register_file_read_batch_random
ibex_sca_register_file_read_fvsr
ibex_fi_char_sram_static

The host code is located in lowRISC/ot-sca#349

This commit adds the command handler for: - ibex_sca_tl_write_batch_fvsr - ibex_sca_tl_write_batch_fvsr_fix_address - ibex_sca_tl_write_batch_random - ibex_sca_tl_write_batch_random_fix_address - ibex_sca_tl_write_fvsr - ibex_sca_tl_write_random - ibex_sca_tl_read_batch_fvsr - ibex_sca_tl_read_batch_fvsr_fix_address - ibex_sca_tl_read_batch_random - ibex_sca_tl_read_batch_random_fix_address - ibex_sca_tl_read_fvsr - ibex_sca_tl_read_random - ibex_sca_register_file_write_batch_fvsr - ibex_sca_register_file_write_batch_random - ibex_sca_register_file_write_fvsr - ibex_sca_register_file_write_random - ibex_sca_register_file_read_batch_fvsr - ibex_sca_register_file_read_batch_random - ibex_sca_register_file_read_fvsr The device code is located in lowRISC/opentitan#22272 Signed-off-by: Pascal Nasahl <[email protected]>

This commit adds the command handler for: - ibex_sca_tl_write_batch_fvsr - ibex_sca_tl_write_batch_fvsr_fix_address - ibex_sca_tl_write_batch_random - ibex_sca_tl_write_batch_random_fix_address - ibex_sca_tl_write_fvsr - ibex_sca_tl_write_random - ibex_sca_tl_read_batch_fvsr - ibex_sca_tl_read_batch_fvsr_fix_address - ibex_sca_tl_read_batch_random - ibex_sca_tl_read_batch_random_fix_address - ibex_sca_tl_read_fvsr - ibex_sca_tl_read_random - ibex_sca_register_file_write_batch_fvsr - ibex_sca_register_file_write_batch_random - ibex_sca_register_file_write_fvsr - ibex_sca_register_file_write_random - ibex_sca_register_file_read_batch_fvsr - ibex_sca_register_file_read_batch_random - ibex_sca_register_file_read_fvsr - ibex_sca_register_file_read_random - ibex_fi_char_sram_write The device code is located in lowRISC/opentitan#22272 Signed-off-by: Pascal Nasahl <[email protected]>

johannheyszl

Thanks @nasahlpa

timothytrippel

Dropped a few more comments in addition to the style comments I dropped in #22310 and #22269.

sw/device/tests/crypto/cryptotest/firmware/ibex_sca.c

timothytrippel · 2024-03-28T15:21:06Z

sw/device/tests/crypto/cryptotest/firmware/ibex_sca.c

+
+  for (int i = 0; i < uj_data.num_iterations; i++) {
+    // Initialize temporary registers with reference values.
+    asm volatile("mv x5, %0" : : "r"(0));


move this to a static function and share across the file? (DRY principle)

You mean the generation of the random values? I've created a two static functions for generating random and FvsR values instead of repeating the same code.

I mean this asm block that initializes temp registers with values

I am not sure if adding a function that initializes x5, x6, x7, x28, x29, x30 works. When having a function call to such an initialization function, is it guaranteed that these registers contain the values I am expecting after returning from the function? These registers are temporary registers.

sorry, inline function or macro? something to help keep everything in sync over time that still satisfies your constraints. I.e., if you change something, you have to change it everywhere, makes things hard to maintain. Unless there are SCA reasons you have like you stated below.

Done, thanks :)

sw/device/tests/crypto/cryptotest/firmware/ibex_sca.c

timothytrippel · 2024-03-29T00:06:58Z

sw/device/tests/crypto/cryptotest/firmware/ibex_sca.c

+
+  for (int i = 0; i < uj_data.num_iterations; i++) {
+    // Initialize temporary registers with reference values.
+    asm volatile("mv x5, %0" : : "r"(0));


I mean this asm block that initializes temp registers with values

This commit adds the following new FI and SCA ibex tests: - ibex_sca_tl_write_batch_fvsr - ibex_sca_tl_write_batch_fvsr_fix_address - ibex_sca_tl_write_batch_random - ibex_sca_tl_write_batch_random_fix_address - ibex_sca_tl_write_fvsr - ibex_sca_tl_write_random - ibex_sca_tl_read_batch_fvsr - ibex_sca_tl_read_batch_fvsr_fix_address - ibex_sca_tl_read_batch_random - ibex_sca_tl_read_batch_random_fix_address - ibex_sca_tl_read_fvsr - ibex_sca_tl_read_random - ibex_sca_register_file_write_batch_fvsr - ibex_sca_register_file_write_batch_random - ibex_sca_register_file_write_fvsr - ibex_sca_register_file_write_random - ibex_sca_register_file_read_batch_fvsr - ibex_sca_register_file_read_batch_random - ibex_sca_register_file_read_fvsr - ibex_sca_register_file_read_random - ibex_fi_char_sram_static The host code is located in lowRISC/ot-sca#349. Signed-off-by: Pascal Nasahl <[email protected]>

This commit adds the command handler for the ibex_char_sram_write test. The device PR is located in lowRISC/opentitan#22272 Signed-off-by: Pascal Nasahl <[email protected]>

This commit adds the command handler for: - ibex_sca_tl_write_batch_fvsr - ibex_sca_tl_write_batch_fvsr_fix_address - ibex_sca_tl_write_batch_random - ibex_sca_tl_write_batch_random_fix_address - ibex_sca_tl_write_fvsr - ibex_sca_tl_write_random - ibex_sca_tl_read_batch_fvsr - ibex_sca_tl_read_batch_fvsr_fix_address - ibex_sca_tl_read_batch_random - ibex_sca_tl_read_batch_random_fix_address - ibex_sca_tl_read_fvsr - ibex_sca_tl_read_random - ibex_sca_register_file_write_batch_fvsr - ibex_sca_register_file_write_batch_random - ibex_sca_register_file_write_fvsr - ibex_sca_register_file_write_random - ibex_sca_register_file_read_batch_fvsr - ibex_sca_register_file_read_batch_random - ibex_sca_register_file_read_fvsr - ibex_sca_register_file_read_random - ibex_fi_char_sram_write The device code is located in lowRISC/opentitan#22272 Signed-off-by: Pascal Nasahl <[email protected]>

nasahlpa · 2024-04-10T05:14:48Z

Sorry for the long delay with the rebase - after the rebase the firmware was too large for the memory and I had to separate the pen. tests from the crypto tests (see #22450). I hope we can merge this soon - the failing tests in CI are not related to this PR.

github-actions · 2024-04-10T22:44:18Z

Backport failed for master, because it was unable to cherry-pick the commit(s).

Please cherry-pick the changes locally and resolve any conflicts.

git fetch origin master
git worktree add -d .worktree/backport-22272-to-master origin/master
cd .worktree/backport-22272-to-master
git switch --create backport-22272-to-master
git cherry-pick -x 773655502cf220ab0035bd2b5f924d7153be8e71

This commit adds the command handler for: - ibex_sca_tl_write_batch_fvsr - ibex_sca_tl_write_batch_fvsr_fix_address - ibex_sca_tl_write_batch_random - ibex_sca_tl_write_batch_random_fix_address - ibex_sca_tl_write_fvsr - ibex_sca_tl_write_random - ibex_sca_tl_read_batch_fvsr - ibex_sca_tl_read_batch_fvsr_fix_address - ibex_sca_tl_read_batch_random - ibex_sca_tl_read_batch_random_fix_address - ibex_sca_tl_read_fvsr - ibex_sca_tl_read_random - ibex_sca_register_file_write_batch_fvsr - ibex_sca_register_file_write_batch_random - ibex_sca_register_file_write_fvsr - ibex_sca_register_file_write_random - ibex_sca_register_file_read_batch_fvsr - ibex_sca_register_file_read_batch_random - ibex_sca_register_file_read_fvsr - ibex_sca_register_file_read_random - ibex_fi_char_sram_write The device code is located in lowRISC/opentitan#22272 and the binary was compiled from lowRISC/opentitan@7f7dbbc Signed-off-by: Pascal Nasahl <[email protected]>

This commit adds the command handler for the ibex_char_sram_write test. The device PR is located in lowRISC/opentitan#22272 Signed-off-by: Pascal Nasahl <[email protected]>

nasahlpa force-pushed the ibex_sca_batch branch from eb449e6 to c707694 Compare March 27, 2024 08:10

nasahlpa mentioned this pull request Mar 27, 2024

[capture] Batch mode for Ibex SCA lowRISC/ot-sca#349

Merged

nasahlpa force-pushed the ibex_sca_batch branch from c707694 to 9813613 Compare March 27, 2024 14:42

nasahlpa marked this pull request as ready for review March 27, 2024 15:30

nasahlpa requested a review from a team as a code owner March 27, 2024 15:30

nasahlpa requested review from jadephilipoom, luismarques, vogelpi and johannheyszl and removed request for a team and jadephilipoom March 27, 2024 15:31

nasahlpa added the CherryPick:master This PR should be cherry-picked to master label Mar 27, 2024

johannheyszl approved these changes Mar 28, 2024

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timothytrippel reviewed Mar 28, 2024

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nasahlpa force-pushed the ibex_sca_batch branch 2 times, most recently from 6cc7c4b to b018806 Compare March 28, 2024 18:52

timothytrippel self-requested a review March 28, 2024 23:56

timothytrippel reviewed Mar 29, 2024

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nasahlpa force-pushed the ibex_sca_batch branch from b018806 to 1faf819 Compare March 29, 2024 09:56

timothytrippel self-requested a review March 29, 2024 19:06

timothytrippel approved these changes Mar 29, 2024

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nasahlpa force-pushed the ibex_sca_batch branch 3 times, most recently from a561652 to 97389d8 Compare April 5, 2024 09:48

nasahlpa mentioned this pull request Apr 9, 2024

[fi] Add SRAM static cmd handler lowRISC/ot-sca#357

Merged

nasahlpa force-pushed the ibex_sca_batch branch from 97389d8 to 7736555 Compare April 9, 2024 12:48

timothytrippel merged commit 7f7dbbc into lowRISC:earlgrey_es_sival Apr 10, 2024
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[pentest] Batch mode for Ibex SCA #22272

[pentest] Batch mode for Ibex SCA #22272

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github-actions bot commented Apr 10, 2024

[pentest] Batch mode for Ibex SCA #22272

[pentest] Batch mode for Ibex SCA #22272

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