[spi_device] Add support for 1r1w RAMs and parity init

hw/ip/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv

@@ -925,8 +925,10 @@ package flash_ctrl_reg_pkg;
   // Window parameters for core interface
   parameter logic [CoreAw-1:0] FLASH_CTRL_PROG_FIFO_OFFSET = 9'h 1b0;
   parameter int unsigned       FLASH_CTRL_PROG_FIFO_SIZE   = 'h 4;
+  parameter int unsigned       FLASH_CTRL_PROG_FIFO_IDX    = 0;
   parameter logic [CoreAw-1:0] FLASH_CTRL_RD_FIFO_OFFSET = 9'h 1b4;
   parameter int unsigned       FLASH_CTRL_RD_FIFO_SIZE   = 'h 4;
+  parameter int unsigned       FLASH_CTRL_RD_FIFO_IDX    = 1;
 
   // Register index for core interface
   typedef enum int {

hw/ip/hmac/rtl/hmac_reg_pkg.sv

@@ -253,6 +253,7 @@ package hmac_reg_pkg;
   // Window parameters
   parameter logic [BlockAw-1:0] HMAC_MSG_FIFO_OFFSET = 12'h 800;
   parameter int unsigned        HMAC_MSG_FIFO_SIZE   = 'h 800;
+  parameter int unsigned        HMAC_MSG_FIFO_IDX    = 0;
 
   // Register index
   typedef enum int {

hw/ip/kmac/rtl/kmac_reg_pkg.sv

@@ -377,8 +377,10 @@ package kmac_reg_pkg;
   // Window parameters
   parameter logic [BlockAw-1:0] KMAC_STATE_OFFSET = 12'h 400;
   parameter int unsigned        KMAC_STATE_SIZE   = 'h 200;
+  parameter int unsigned        KMAC_STATE_IDX    = 0;
   parameter logic [BlockAw-1:0] KMAC_MSG_FIFO_OFFSET = 12'h 800;
   parameter int unsigned        KMAC_MSG_FIFO_SIZE   = 'h 800;
+  parameter int unsigned        KMAC_MSG_FIFO_IDX    = 1;
 
   // Register index
   typedef enum int {

hw/ip/otbn/rtl/otbn_reg_pkg.sv

@@ -307,8 +307,10 @@ package otbn_reg_pkg;
   // Window parameters
   parameter logic [BlockAw-1:0] OTBN_IMEM_OFFSET = 16'h 4000;
   parameter int unsigned        OTBN_IMEM_SIZE   = 'h 1000;
+  parameter int unsigned        OTBN_IMEM_IDX    = 0;
   parameter logic [BlockAw-1:0] OTBN_DMEM_OFFSET = 16'h 8000;
   parameter int unsigned        OTBN_DMEM_SIZE   = 'h c00;
+  parameter int unsigned        OTBN_DMEM_IDX    = 1;
 
   // Register index
   typedef enum int {

hw/ip/otp_ctrl/rtl/otp_ctrl_reg_pkg.sv

@@ -579,6 +579,7 @@ package otp_ctrl_reg_pkg;
   // Window parameters for core interface
   parameter logic [CoreAw-1:0] OTP_CTRL_SW_CFG_WINDOW_OFFSET = 13'h 1000;
   parameter int unsigned       OTP_CTRL_SW_CFG_WINDOW_SIZE   = 'h 800;
+  parameter int unsigned       OTP_CTRL_SW_CFG_WINDOW_IDX    = 0;
 
   // Register index for core interface
   typedef enum int {

hw/ip/prim/lint/prim_ram_1r1w.waiver

@@ -0,0 +1,8 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# waiver file for prim_ram_1r1w
+
+waive -rules {STAR_PORT_CONN_USE} -location {prim_ram_1r1w.sv} -regexp {.*wild card port connection encountered on instance.*} \
+      -comment "Generated prims may have wildcard connections."

hw/ip/prim/prim_ram_1r1w.core

@@ -0,0 +1,50 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+name: "lowrisc:prim:ram_1r1w"
+description: "Random-access memory with 1 read-only port and 1 write-only port"
+filesets:
+  primgen_dep:
+    depend:
+      - lowrisc:prim:prim_pkg
+      - lowrisc:prim:ram_2p_pkg
+      - lowrisc:prim:primgen
+
+
+  files_verilator_waiver:
+    depend:
+      # common waivers
+      - lowrisc:lint:common
+    files:
+    file_type: vlt
+
+  files_ascentlint_waiver:
+    depend:
+      # common waivers
+      - lowrisc:lint:common
+    files:
+      - lint/prim_ram_1r1w.waiver
+    file_type: waiver
+
+  files_veriblelint_waiver:
+    depend:
+      # common waivers
+      - lowrisc:lint:common
+
+generate:
+  impl:
+    generator: primgen
+    parameters:
+      prim_name: ram_1r1w
+
+targets:
+  default:
+    filesets:
+      - tool_verilator   ? (files_verilator_waiver)
+      - tool_ascentlint  ? (files_ascentlint_waiver)
+      - tool_veriblelint ? (files_veriblelint_waiver)
+      - primgen_dep
+    generate:
+      - impl

hw/ip/prim/prim_ram_1r1w_adv.core

@@ -0,0 +1,19 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+name: "lowrisc:prim:ram_1r1w_adv:0.1"
+description: "Two-port (1 read-only port, 1 write-only port) RAM primitive with advanced features"
+filesets:
+  files_rtl:
+    depend:
+      - lowrisc:prim:ram_1r1w_async_adv
+    files:
+      - rtl/prim_ram_1r1w_adv.sv
+    file_type: systemVerilogSource
+
+targets:
+  default:
+    filesets:
+      - files_rtl

hw/ip/prim/prim_ram_1r1w_async_adv.core

@@ -0,0 +1,22 @@
+CAPI=2:
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+name: "lowrisc:prim:ram_1r1w_async_adv:0.1"
+description: "Asynchronous two-port (1 read-only port, 1 write-only port) RAM primitive with advanced features"
+filesets:
+  files_rtl:
+    depend:
+      - lowrisc:prim:assert
+      - lowrisc:prim:util
+      - lowrisc:prim:secded
+      - lowrisc:prim:ram_1r1w
+    files:
+      - rtl/prim_ram_1r1w_async_adv.sv
+    file_type: systemVerilogSource
+
+targets:
+  default:
+    filesets:
+      - files_rtl

hw/ip/prim/rtl/prim_ram_1r1w_adv.sv

@@ -0,0 +1,83 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Two-Port SRAM Wrapper
+//
+// Supported configurations:
+// - ECC for 32b and 64b wide memories with no write mask
+//   (Width == 32 or Width == 64, DataBitsPerMask is ignored).
+// - Byte parity if Width is a multiple of 8 bit and write masks have Byte
+//   granularity (DataBitsPerMask == 8).
+//
+// Note that the write mask needs to be per Byte if parity is enabled. If ECC is enabled, the write
+// mask cannot be used and has to be tied to {Width{1'b1}}.
+
+`include "prim_assert.sv"
+
+module prim_ram_1r1w_adv import prim_ram_2p_pkg::*; #(
+  parameter  int Depth                = 512,
+  parameter  int Width                = 32,
+  parameter  int DataBitsPerMask      = 1,  // Number of data bits per bit of write mask
+  parameter      MemInitFile          = "", // VMEM file to initialize the memory with
+
+  // Configurations
+  parameter  bit EnableECC            = 0, // Enables per-word ECC
+  parameter  bit EnableParity         = 0, // Enables per-Byte Parity
+  parameter  bit EnableInputPipeline  = 0, // Adds an input register (read latency +1)
+  parameter  bit EnableOutputPipeline = 0, // Adds an output register (read latency +1)
+
+  // This switch allows to switch to standard Hamming ECC instead of the HSIAO ECC.
+  // It is recommended to leave this parameter at its default setting (HSIAO),
+  // since this results in a more compact and faster implementation.
+  parameter bit HammingECC            = 0,
+
+  localparam int Aw                   = prim_util_pkg::vbits(Depth)
+) (
+  input                    clk_i,
+  input                    rst_ni,
+
+  // Port A can only write
+  input                    a_req_i,
+  input        [Aw-1:0]    a_addr_i,
+  input        [Width-1:0] a_wdata_i,
+  input        [Width-1:0] a_wmask_i,  // cannot be used with ECC, tie to 1 in that case
+
+  // Port B can only read
+  input                    b_req_i,
+  input        [Aw-1:0]    b_addr_i,
+  output logic [Width-1:0] b_rdata_o,
+  output logic             b_rvalid_o, // read response (b_rdata_o) is valid
+  output logic [1:0]       b_rerror_o, // Bit1: Uncorrectable, Bit0: Correctable
+
+  input ram_2p_cfg_t       cfg_i
+);
+
+  prim_ram_1r1w_async_adv #(
+    .Depth               (Depth),
+    .Width               (Width),
+    .DataBitsPerMask     (DataBitsPerMask),
+    .MemInitFile         (MemInitFile),
+    .EnableECC           (EnableECC),
+    .EnableParity        (EnableParity),
+    .EnableInputPipeline (EnableInputPipeline),
+    .EnableOutputPipeline(EnableOutputPipeline),
+    .HammingECC          (HammingECC)
+  ) i_prim_ram_1r1w_async_adv (
+    .clk_a_i(clk_i),
+    .rst_a_ni(rst_ni),
+    .clk_b_i(clk_i),
+    .rst_b_ni(rst_ni),
+    .a_req_i,
+    .a_addr_i,
+    .a_wdata_i,
+    .a_wmask_i,
+    .b_req_i,
+    .b_addr_i,
+    .b_rdata_o,
+    .b_rvalid_o,
+    .b_rerror_o,
+    .cfg_i
+  );
+
+endmodule : prim_ram_1r1w_adv