[hw,rv_core_ibex,rtl] Increase upper bound for cycles to wait in IbexIcacheScrambleKeyRequestAfterFenceI_A

[Razer6]

When OpenOCD issues a fence.i instruction as part of executing a program buffer through the DM the following assertion triggers:

[11-28 08:20:01] -I- xmsim: *E,ASRTST (/work/opentitan.integrated/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv,976): (time 10638803280 PS) Assertion top.u_rv_core_ibex.gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A has failed (in 11 cycles)
[11-28 08:20:01] -I- UVM_ERROR ../../../opentitan.integrated/hw/ip/rv_core_ibex/rtl/rv_core_ibex.sv(976) @ 10638803280000: reporter [ASSERT FAILED] IbexIcacheScrambleKeyRequestAfterFenceI_A

I see upstream has increased this to 14 from 10 - 4e615de

We found that 14 wasn’t sufficient, but 20 works reliably.

[andreaskurth]

@Razer6: Quick lint fails because the first line of the commit message is too long