[pwrmgr] D2(S) Signoff

[msfschaffner]

Description

Ensure D2(S) signoff criteria are still maintained (this is not a focus area block).

[matutem]

pwrmgr D2(S) Signoff

This is not a focus area block.

Commits since Earlgrey-ES tapeout

$ git rev-parse --short HEAD
af85dad7af
$ git log Earlgrey-M2.5.2-RC0..af85dad7af --oneline -- hw/ip/pwrmgr hw/ip_templates/pwrmgr

• dd11737 [doc,pwrmgr] Document wakeup signal requirements
  • Document-only clarification
• b16179d [ipgen,rstmgr] Fix BUILD files
  • Change related to ipgen transition
• ab4b36f [ipgen,rstmgr] Fix paths to rstmgr in md files
  • Change related to rstmgr ipgen transition
• ce648ca [ipgen.pwrmgr] Change core files to vlnv naming and label as virtual
  • Fix related to pwrmgr ipgen transition
• 4a9a881 [topgen] Pass topname key/value pair to ipgen
  • Fix related to ipgen transition
• da087bb [rtl,pwrmgr] Fix escalation timeout persistence
  • Fixes RTL issue [rtl,pwrmgr] escalation timeout should persist #20516 needed for PROD
• de31bdf [reggen] Remove the devmode input
  • devmode was tied to 1'b1 and the change is a net improvement with no functional impact
• 963a500 [doc] Minor tweak to md sanitisation code
  • Documentation-only change
• 748235c [dv,pwrmgr] Fix pwrmgr_escalation_timeout test
  • Fixes the test that verifies issue [rtl,pwrmgr] escalation timeout should persist #20516
• 729f744 [dv/pwrmgr] Add escalation_timeout test
  • Adds a test to verify [rtl,pwrmgr] escalation timeout should persist #20516
• c87db05 [pwrmgr,ipgen] Remove the hw/ip/pwrmgr and their autogen files
  • Change related to pwrmgr ipgen transition
• 7215f8d [pwrmgr,ipgen] Fix hjson files
  • Change related to pwrmgr ipgen transition
• 78c7edd [pwrmgr,ipgen] Fix pwrmgr template and autogen core files
  • Change related to pwrmgr ipgen transition
• 988b584 [pwrmgr,ipgen] Fix BUILD files
  • Change related to pwrmgr ipgen transition
• 3f88a55 [pwrmgr,ipgen] Generate pwrmgr ip_autogen files with topgen
  • Change related to pwrmgr ipgen transition
• 8034e00 [pwrmgr,ipgen] Turn a few more files into templates
  • Change related to pwrmgr ipgen transition
• a8529ce [pwrmgr,ipgen] Copy all hw/ip/pwrmgr files to ip_templates
  • Change related to pwrmgr ipgen transition
• c288cc3 [pwrmge,ip_gen] Add tpldesc hjson file
  • Change related to pwrmgr ipgen transition
• 77278de [pwrmgr] Replace tab with spaces in test plan
  • hjson formatting change
• 709d4e7 [doc/pwrmgr] Improve theory of operation doc
  • Documentation-only improvement
• 9e006e2 [sival,pwrmgr] Add features in pwrmgr.hjson.tpl
  • Adds features needed for the sival flow
• 1b16ca2 [reggen] Add mubi support SWAccess that sets/clears a reg
  • Fixes a bug on MuBi CSR RTL
• f4f5d98 [dv/pwrmgr] Allow transitions to invalid fsm state
  • DV fix for SVA
• 59f8142 [doc] Moved badges over to using hosted images
  • Documentation-only improvement
• 13c6152 [doc] pwrmgr registers and interfaces now use CMDGEN
  • Documentation-only improvement
• f7edbbb [pwrmgr,dv] Correct name of disabled assertion
  • DV fix for SVA
• 51d31a1 [dv/pwrmgr] Complete SVAs for rom integrity checks
  • DV fix for SVA issue [dv/pwrmgr] verify rom integrity check transitions #18236
• 7688e71 [reggen] Add initial support for version and cip_id hjson fields
  • RTL fix for issue [reggen] RFC: support for block version registers #15333
• fbd888e Revert "[reggen] Add CIP_IDs and bump all major versions"
  • Reverts the change below
• 0ba10b3 [reggen] Add CIP_IDs and bump all major versions
  • This change was reverted
• 9a61b02 [pwrmgr] Fix xcelium compile error
  • Fix for xcelium, no functional change
• 143faa6 [pwrmgr] Synchronize lc signals
  • DV fix for SVA
• e47df29 [misc] Use lc_tx_t testing functions at endpoints
  • RTL cleanup that doesn't affect functionality

Issues closed since the Earlgrey-ES tapeout

• [chip-test] chip_sw_pwrmgr_escalation_reset #21451 [chip-test, pwrmgr] chip_sw_pwrmgr_escalation_reset Component:ChipLevelTest IP:pwrmgr Priority:P2 SiVal:Autogen

• [chip-test] chip_sw_pwrmgr_b2b_sleep_reset_req #21450 [chip-test, pwrmgr] chip_sw_pwrmgr_b2b_sleep_reset_req Component:ChipLevelTest IP:pwrmgr Priority:P2 SiVal:Autogen

• [chip-test] chip_sw_pwrmgr_sleep_power_glitch_reset #21449 [chip-test, pwrmgr] chip_sw_pwrmgr_sleep_power_glitch_reset Component:ChipLevelTest IP:pwrmgr Priority:P2 SiVal:Autogen

• [chip-test] chip_sw_pwrmgr_deep_sleep_power_glitch_reset #21448 [chip-test, pwrmgr] chip_sw_pwrmgr_deep_sleep_power_glitch_reset Component:ChipLevelTest IP:pwrmgr Priority:P2 SiVal:Autogen

• [chip-test] chip_sw_pwrmgr_random_sleep_power_glitch_reset #21447 [chip-test, pwrmgr] chip_sw_pwrmgr_random_sleep_power_glitch_reset Component:ChipLevelTest IP:pwrmgr Priority:P2 SiVal:Autogen

• [chip-test] chip_sw_pwrmgr_main_power_glitch_reset #21446 [chip-test, pwrmgr] chip_sw_pwrmgr_main_power_glitch_reset Component:ChipLevelTest IP:pwrmgr Priority:P2 SiVal:Autogen

• [chip-test] chip_sw_pwrmgr_aon_power_glitch_reset #21445 [chip-test, pwrmgr] chip_sw_pwrmgr_aon_power_glitch_reset Component:ChipLevelTest IP:pwrmgr Priority:P2 SiVal:Autogen

• [chip-test] chip_sw_sensor_ctrl_deep_sleep_wake_up #21444 [chip-test, pwrmgr] chip_sw_sensor_ctrl_deep_sleep_wake_up Component:ChipLevelTest IP:pwrmgr Priority:P2 SiVal:Autogen

• [chip-test] chip_sw_pwrmgr_normal_sleep_all_wake_ups #21443 [chip-test, pwrmgr] chip_sw_pwrmgr_normal_sleep_all_wake_ups Component:ChipLevelTest IP:pwrmgr Priority:P2 SiVal:Autogen

• [chip-test] chip_sw_pwrmgr_external_full_reset #21442 [chip-test, pwrmgr] chip_sw_pwrmgr_external_full_reset Component:ChipLevelTest IP:pwrmgr Priority:P2 SiVal:Autogen

• [rstmgr] V2(S) Signoff #21026 [rstmgr] V2(S) Signoff Component:DV IP:rstmgr

• [clkmgr] V2(S) Signoff #21024 [clkmgr] V2(S) Signoff Component:DV IP:clkmgr

• [lc_ctrl] V2(S) Signoff #21014 [lc_ctrl] V2(S) Signoff Component:DV IP:lc_ctrl

• [rstmgr] D2(S) Signoff #20991 [rstmgr] D2(S) Signoff Component:RTL IP:rstmgr

• [clkmgr] D2(S) Signoff #20989 [clkmgr] D2(S) Signoff Component:RTL IP:clkmgr

• [lc_ctrl] D2(S) Signoff #20979 [lc_ctrl] D2(S) Signoff Component:RTL IP:lc_ctrl

• [doc,pwrmgr] Improve documentation of wakeup recording #20858 [doc,pwrmgr] Improve documentation of wakeup recording Component:Doc

• [ip,doc] Fix inaccurate references to reset behavior #20700 [ip,doc] Fix inaccurate references to reset behavior Component:Doc Milestone:V3 Priority:P2

• [sival,test] Flakiness in detecting PASS! in Rust test harnesses #20580 [sival,test] Flakiness in detecting PASS! in Rust test harnesses Component:ChipLevelTest Component:SiliconValidation Help Wanted Priority:P1 Type:Bug

• [rtl,pwrmgr] escalation timeout should persist #20516 [rtl,pwrmgr] escalation timeout should persist Component:RTL Component:Security Earlgrey-PROD Candidate IP:pwrmgr Priority:P1

• [top_darjeeling] watch dog reset should be mapped to bit 0 #20415 [top_darjeeling] watch dog reset should be mapped to bit 0 Component:Darjeeling Component:DV Component:TestTriage

• [sysrst_ctrl] Unable to reset OT #20392 [sysrst_ctrl] Unable to reset OT Priority:P1

• [dv,pwrmgr] Add test for escalation_timeout testpoint #20158 [dv,pwrmgr] Add test for escalation_timeout testpoint Component:DV Earlgrey-PROD Candidate

• [chip-test] chip_sw_pwrmgr_random_sleep_all_reset_reqs #20135 [chip-test] chip_sw_pwrmgr_random_sleep_all_reset_reqs Component:ChipLevelTest Component:SiliconValidation

• [chip-test] chip_sw_pwrmgr_sleep_por_reset #20134 [chip-test] chip_sw_pwrmgr_sleep_por_reset Component:ChipLevelTest Component:SiliconValidation

• [chip-test] chip_sw_pwrmgr_deep_sleep_por_reset #20133 [chip-test] chip_sw_pwrmgr_deep_sleep_por_reset Component:ChipLevelTest Component:SiliconValidation

• [chip-test] chip_sw_pwrmgr_random_sleep_all_wake_ups #20058 [chip-test] chip_sw_pwrmgr_random_sleep_all_wake_ups Component:ChipLevelTest

• [chip-test] chip_sw_sysrst_ctrl_combo_reset #19858 [chip-test] chip_sw_sysrst_ctrl_combo_reset Component:ChipLevelTest Component:SiliconValidation IP:sysrst_ctrl SiVal:BazelLinkNeeded SiVal:draft/WIP

• [top_englishbreakfast,util] Fix paths to ip-specific ips in prepare_sw.py #19819 [top_englishbreakfast,util] Fix paths to ip-specific ips in prepare_sw.py

• [top_level,tests] Convert sim_dv sysrst_ctrl test to use opentitantool #19403 [top_level,tests] Convert sim_dv sysrst_ctrl test to use opentitantool Component:ChipLevelTest Earlgrey-PROD Triaged

• [pwrmgr/sram_ctrl] Use synchronizers on all LC signals #19051 [pwrmgr/sram_ctrl] Use synchronizers on all LC signals IP:pwrmgr IP:sram_ctrl Priority:P1 Type:Bug

• [test-triage] rom_e2e_*  #18696 [test-triage] rom_e2e_* Component:ChipLevelTest Component:TestTriage

• [i2c] Unexpected data in ACQ FIFO after deep sleep wakeup #18510 [i2c] Unexpected data in ACQ FIFO after deep sleep wakeup Earlgrey-PROD Candidate IP:i2c Priority:P2

• [aon_timer, rtl/doc] No wakeup signalled on watchdog bite if it occurs before bark #18341 [aon_timer, rtl/doc] No wakeup signalled on watchdog bite if it occurs before bark Component:Doc IP:aon_timer

• [dv/pwrmgr] verify rom integrity check transitions #18236 [dv/pwrmgr] verify rom integrity check transitions Component:DV

• [top_darjeeling] fake pinmux or direct connection #17085 [top_darjeeling] fake pinmux or direct connection Component:Darjeeling

• [ci] Airgapped builds failing #16960 [ci] Airgapped builds failing Component:CI Type:Bug

• [pwrmgr] Potential improvement on escalation path to avoid crossing slow FSM #16735 [pwrmgr] Potential improvement on escalation path to avoid crossing slow FSM Earlgrey-PROD Candidate Hotlist:Security IP:pwrmgr

• [dv/cdc] Enable CDC instrumentation in all ips #16689 [dv/cdc] Enable CDC instrumentation in all ips Component:DV Priority:P2 Triaging:MultipleBlocks

• Flow error that dc is unsupported for job runtime extraction #16562 Flow error that dc is unsupported for job runtime extraction

• [escalation / rma entry] Better cross handling in the future #14867 [escalation / rma entry] Better cross handling in the future IP:alert_handler IP:lc_ctrl IP:pwrmgr Triaging:MultipleBlocks Type:FutureRelease

Currently open issues

• [sival,triag] Some SiVal ROM_EXT are broken #21706 [sival,triag] Some SiVal ROM_EXT are broken

• [chip-test] Incomplete SiVal Stage 1 and 2 tests #21222 [chip-test] Incomplete SiVal Stage 1 and 2 tests

  • pwrmgr tests are done

• [sival] test_locked_all_tests #21083 [sival] test_locked_all_tests

  • pwrmgr tests are done

• [sival] test_unlocked1_all_tests #21081 [sival] test_unlocked1_all_tests

  • pwrmgr tests are done

• [sival] test_unlocked_all_tests #21076 [sival] test_unlocked_all_tests

  • pwrmgr tests are done

• [sival] raw_all_tests #21075 [sival] raw_all_tests

  • pwrmgr tests are done

• [sival] dev_all_tests #21074 [sival] dev_all_tests

  • pwrmgr tests are done

• [pwrmgr] V2(S) Signoff #21025 [pwrmgr] V2(S) Signoff Component:DV IP:pwrmgr

• [flash_ctrl] V2(S) Signoff #21012 [flash_ctrl] V2(S) Signoff Component:DV IP:flash_ctrl

  • This is unrelated, probably bad labelling

• [pwrmgr] D2(S) Signoff #20990 [pwrmgr] D2(S) Signoff Component:RTL IP:pwrmgr

• [otp_ctrl] D2S Signoff #20983 [otp_ctrl] D2 Signoff Component:RTL IP:otp_ctrl

  • This is unrelated, bad labelling?

• [sival,sensor_ctrl] Fix unexpected alert 5 #20798 [sival,sensor_ctrl] Fix unexpected alert 5 Component:RTL Component:SiliconValidation

  • Unrelated to pwrmgr

• [rtl,pwrmgr] escalation reset requests should not be delayed so much #20518 [rtl,pwrmgr] escalation reset requests should not be delayed so much Component:RTL Component:Security Earlgrey-PROD Candidate IP:pwrmgr Priority:P2

  • To be done, has no counter-measure impact

• [sival] prod_all_tests #20194 [sival] prod_all_tests

  • pwrmgr tests are done

• [chip-test] chip_sw_sysrst_ctrl_ulp_wakeup #19861 [chip-test] chip_sw_sysrst_ctrl_ulp_wakeup Component:ChipLevelTest Component:SiliconValidation IP:sysrst_ctrl SiVal:BazelLinkNeeded SiVal:draft/WIP

  • Does not affect pwrmgr

• [doc,dif] Fix link in dif header files #19810 [doc,dif] Fix link in dif header files

  • Documentation-only

• [bazel, dvsim] Convert dvsim-executed tests to the new rules #19797 [bazel, dvsim] Convert dvsim-executed tests to the new rules Earlgrey-PROD Triaged Priority:P1 SW:Build System Type:Task

  • All pwrmgrs tests are done

• [pwrmgr] Error FSM state is not observable in pwrmgr_fsm #19124 [pwrmgr] Error FSM state is not observable in pwrmgr_fsm Earlgrey-PROD Candidate Priority:P2

  • There is an alternative way to implement the assertion for formal.

• [aon_timer] Consider requirements for clk_aon_i vs clk_i #19059 [aon_timer] Consider requirements for clk_aon_i vs clk_i Earlgrey-PROD Candidate IP:aon_timer Priority:P2 Type:FutureRelease

  • It has no impact on pwrmgr

• [doc] AON Timer wdog bite reset missing sw initialization documentation #18513 [doc] AON Timer wdog bite reset missing sw initialization documentation Earlgrey-PROD Candidate

  • Documentation-only issue.

• [dv/mem_bkdr_util] Improve memory write performance #17086 [dv/mem_bkdr_util] Improve memory write performance Component:DV Earlgrey-PROD Candidate Type:Icebox

  • No impact on D/V2(S)

• [chip-test] Move C tests without external host from tests/sim_dv/ to tests/ #16636 [chip-test] Move C tests without external host from tests/sim_dv/ to tests/ Component:ChipLevelTest Earlgrey-PROD Triaged IP:alert_handler IP:csrng IP:entropy_src IP:flash_ctrl IP:lc_ctrl IP:otp_ctrl IP:pwrmgr IP:sram_ctrl Priority:P3 Subsystem:Entropy Triaging:MultipleBlocks Type:Enhancement

  • pwrmgr tests are done

• [dv/rstmgr] Apply different reset kinds where applicable #16148 [dv/rstmgr] Apply different reset kinds where applicable Component:DV Earlgrey-PROD Candidate IP:rstmgr Priority:P2

  • It does not apply to pwrmgr

• [rtl,reset] Improve handling of main domain power glitches #15986 [rtl,reset] Improve handling of main domain power glitches Component:DV Component:RTL Earlgrey-PROD Triaged IP:ast IP:pwrmgr IP:rstmgr Type:FutureRelease

  • This is not staged for PROD

• [chip/prim_esc_receiver] check if prim_esc_receiver is out-of-sync #14887 [chip/prim_esc_receiver] check if prim_esc_receiver is out-of-sync Component:DV Earlgrey-PROD Candidate IP:alert_handler IP:prim IP:pwrmgr Priority:P2 TOP:earlgrey

  • I think this should not block D/V2(S)

• [top/doc] Autogenerated tables for top-specific IP #12848 [top/doc] Autogenerated tables for top-specific IP Component:Doc Earlgrey-PROD Triaged IP:alert_handler IP:clkmgr IP:pinmux IP:pwrmgr IP:rstmgr IP:rv_plic Triaging:MultipleBlocks Type:Cleanup Type:FutureRelease Type:Icebox

  • Documentation-only issue

• [dv/exclusions] Change handling of full-chip exclusions #11520 [dv/exclusions] Change handling of full-chip exclusions Component:DV Earlgrey-PROD Candidate IP:clkmgr IP:pwrmgr IP:rstmgr Priority:P3

  • Not a D/V2(S) issue

• [rom_ext] Possibly check ROM digest against a known value? #10323 [rom_ext] Possibly check ROM digest against a known value? Component:Software Earlgrey-PROD Triaged Priority:P3 SW:ROM_EXT

  • No impact on pwrmgr, since it only looks at the result of the checks as reported by rom_ctrl

• [top, doc] Top level documentation for keymgr seed flow #9206 [top, doc] Top level documentation for keymgr seed flow Component:Doc Earlgrey-PROD Triaged IP:flash_ctrl IP:keymgr IP:lc_ctrl IP:otp_ctrl IP:pwrmgr Priority:P4 TOP:earlgrey Triaging:MultipleBlocks

  • Documentation-only issue

• [tracking] Use ipgen to produce templated IPs #8440 [tracking] Use ipgen to produce templated IPs Component:Tooling Earlgrey-PROD Candidate IP:clkmgr IP:flash_ctrl IP:pwrmgr IP:rstmgr Priority:P2 Triaging:MultipleBlocks Type:Cleanup

  • The pwrmgr part of this is done

• [ast] Make ast a comportable module or at least a comportable front-end #7978 [ast] Make ast a comportable module or at least a comportable front-end Component:RTL Earlgrey-PROD Triaged IP:ast Priority:P2 Type:FutureRelease

  • Not pwrmgr related

• [pwrmgr] Documentation update #7612 [pwrmgr] Documentation update Component:Doc Earlgrey-PROD Triaged IP:pwrmgr Priority:P3 Type:Task

  • Documentation-only

• [flash_ctrl] TODO list for open source portion of flash controller #3353 [flash_ctrl] TODO list for open source portion of flash controller Component:RTL Earlgrey-PROD Candidate IP:flash_ctrl Priority:P2 Type:Task

  • Not pwrmgr related

• [topgen] topgen flow #2083 [topgen] topgen flow Component:MultiTop Component:Tooling Earlgrey-PROD Triaged Priority:P3 TOP:earlgrey Type:FutureRelease

  • Not staged for PROD

[msfschaffner]

Thanks for summarizing this @matutem.

I reviewed the RTL changes in more detail above:

• da087bb [rtl,pwrmgr] Fix escalation timeout persistence
  • bugfix that is already tested in DV -> OK
• de31bdf [reggen] Remove the devmode input
  • the alternative mode was never used -> OK
• 1b16ca2 [reggen] Add mubi support SWAccess that sets/clears a reg
  • bugfix in reggen -> OK
• 9a61b02 [pwrmgr] Fix xcelium compile error
  • no functional change -> OK
• 143faa6 [pwrmgr] Synchronize lc signals
  • this cleanup does not affect functionality and is already tested in DV -> OK
• e47df29 [misc] Use lc_tx_t testing functions at endpoints
  • this cleanup does not affect functionality and is already tested in DV -> OK

I believe the only open design issue is #20518, which is an enhancement that intend to look into at PROD.M3, so this should not gate D2S/V2S for now.

The Hjson still lists v1.0.0 D2S, so no change is needed to the Hjson (the interface did not change, hence no version increase is necessary):

opentitan/hw/ip_templates/pwrmgr/data/pwrmgr.hjson.tpl

Lines 34 to 40 in 7e196e6

	{
	version: "1.0.0",
	life_stage: "L1",
	design_stage: "D2S",
	verification_stage: "V2S",
	dif_stage: "S2",
	}