[spi_device] Add params for DPRAM offsets

Add params for the DPRAM offsets so they are available in C headers for software. Signed-off-by: Alexander Williams <[email protected]>
lowRISC · Jan 24, 2024 · f83506b · f83506b
1 parent f554d45
commit f83506b
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Showing 4 changed files with 126 additions and 14 deletions.
diff --git a/hw/ip/spi_device/data/spi_device.hjson b/hw/ip/spi_device/data/spi_device.hjson
@@ -139,6 +139,78 @@
       default: "96"
       local:   "true"
     }
+    { name:    "SramReadBufferOffset"
+      desc:    "Sram eFlash read buffer offset (from egress buffer start). Word size is 32bit width."
+      type:    "int unsigned"
+      default: "0"
+      local:   "true"
+    }
+    { name:    "SramReadBufferDepth"
+      desc:    "Sram eFlash read buffer entries. Word size is 32bit width."
+      type:    "int unsigned"
+      default: "512"
+      local:   "true"
+    }
+    { name:    "SramMailboxOffset"
+      desc:    "Sram mailbox buffer offset (from egress buffer start). Word size is 32bit width."
+      type:    "int unsigned"
+      default: "512"
+      local:   "true"
+    }
+    { name:    "SramMailboxDepth"
+      desc:    "Sram mailbox entries. Word size is 32bit width."
+      type:    "int unsigned"
+      default: "256"
+      local:   "true"
+    }
+    { name:    "SramSfdpOffset"
+      desc:    "Sram SFDP buffer offset (from egress buffer start). Word size is 32bit width."
+      type:    "int unsigned"
+      default: "768"
+      local:   "true"
+    }
+    { name:    "SramSfdpDepth"
+      desc:    "Sram SFDP entries. Word size is 32bit width."
+      type:    "int unsigned"
+      default: "64"
+      local:   "true"
+    }
+    { name:    "SramPayloadOffset"
+      desc:    "Sram payload FIFO offset (from ingress buffer start). Word size is 32bit width."
+      type:    "int unsigned"
+      default: "0"
+      local:   "true"
+    }
+    { name:    "SramPayloadDepth"
+      desc:    "Sram payload FIFO entries. Word size is 32bit width."
+      type:    "int unsigned"
+      default: "64"
+      local:   "true"
+    }
+    { name:    "SramCmdFifoOffset"
+      desc:    "Sram command FIFO offset (from ingress buffer start). Word size is 32bit width."
+      type:    "int unsigned"
+      default: "64"
+      local:   "true"
+    }
+    { name:    "SramCmdFifoDepth"
+      desc:    "Sram command FIFO entries. Word size is 32bit width."
+      type:    "int unsigned"
+      default: "16"
+      local:   "true"
+    }
+    { name:    "SramAddrFifoOffset"
+      desc:    "Sram address FIFO offset (from ingress buffer start). Word size is 32bit width."
+      type:    "int unsigned"
+      default: "80"
+      local:   "true"
+    }
+    { name:    "SramAddrFifoDepth"
+      desc:    "Sram address FIFO entries. Word size is 32bit width."
+      type:    "int unsigned"
+      default: "16"
+      local:   "true"
+    }
     { name:    "NumCmdInfo"
       desc:    "Define the number of Command Info slots."
       type:    "int unsigned"

diff --git a/hw/ip/spi_device/rtl/spi_device_pkg.sv b/hw/ip/spi_device/rtl/spi_device_pkg.sv
@@ -5,6 +5,8 @@
 // Serial Peripheral Interface (SPI) Device module.
 //
 
+`include "prim_assert.sv"
+
 package spi_device_pkg;
 
   // Passthrough Inter-module signals
@@ -397,22 +399,27 @@ package spi_device_pkg;
   parameter int unsigned SramOffsetW = $clog2(SramStrbW);
 
   // Msg region is used for read cmd in Flash and Passthrough region
-  parameter int unsigned SramMsgDepth = 512; // 2kB
+  parameter int unsigned SramMsgDepth = spi_device_reg_pkg::SramReadBufferDepth;
   parameter int unsigned SramMsgBytes = SramMsgDepth * SramStrbW;
 
   // Address Width of a Buffer in bytes
   parameter int unsigned SramBufferBytes = SramMsgBytes / 2; // Double Buffer
   parameter int unsigned SramBufferAw    = $clog2(SramBufferBytes);
 
-  parameter int unsigned SramMailboxDepth = 256; // 1kB for mailbox
+  import spi_device_reg_pkg::SramMailboxDepth;
+  export spi_device_reg_pkg::SramMailboxDepth;
 
   // SPI Flash Discoverable Parameter is for host to get the device
   // information. It is a separate Command. The device provides a region in
   // DPSRAM for SW. The size is 256B
-  parameter int unsigned SramSfdpDepth = 64;
-  parameter int unsigned SramPayloadDepth = 64; // 256B for Program
-  parameter int unsigned SramCmdFifoDepth = 16; // 16 x 1B for Cmd
-  parameter int unsigned SramAddrFifoDepth = 16; // 16 x 4B for Addr
+  import spi_device_reg_pkg::SramSfdpDepth;
+  export spi_device_reg_pkg::SramSfdpDepth;
+  import spi_device_reg_pkg::SramPayloadDepth;
+  export spi_device_reg_pkg::SramPayloadDepth;
+  import spi_device_reg_pkg::SramCmdFifoDepth;
+  export spi_device_reg_pkg::SramCmdFifoDepth;
+  import spi_device_reg_pkg::SramAddrFifoDepth;
+  export spi_device_reg_pkg::SramAddrFifoDepth;
   parameter int unsigned SramTotalDepth = SramMsgDepth + SramMailboxDepth
                                         + SramSfdpDepth + SramPayloadDepth
                                         + SramCmdFifoDepth + SramAddrFifoDepth ;
@@ -478,23 +485,35 @@ package spi_device_pkg;
     sram_addr_t'(SramEgressByteOffset[$clog2(SramDw / 8) +: SramAw]);
   parameter sram_addr_t SramReadBufferIdx  = SramEgressIdx;
   parameter sram_addr_t SramReadBufferSize = sram_addr_t'(SramMsgDepth);
+  `ASSERT_STATIC_IN_PACKAGE(CheckReadBufferOffset,
+      SramReadBufferIdx == spi_device_reg_pkg::SramReadBufferOffset)
 
   parameter sram_addr_t SramMailboxIdx  = SramReadBufferIdx + SramReadBufferSize;
   parameter sram_addr_t SramMailboxSize = sram_addr_t'(SramMailboxDepth);
+  `ASSERT_STATIC_IN_PACKAGE(CheckMailboxOffset,
+      SramMailboxIdx == spi_device_reg_pkg::SramMailboxOffset)
 
   parameter sram_addr_t SramSfdpIdx  = SramMailboxIdx + SramMailboxSize;
   parameter sram_addr_t SramSfdpSize = sram_addr_t'(SramSfdpDepth);
+  `ASSERT_STATIC_IN_PACKAGE(CheckSfdpOffset,
+      SramSfdpIdx == spi_device_reg_pkg::SramSfdpOffset)
 
   parameter sram_addr_t SramIngressIdx =
     sram_addr_t'(SramIngressByteOffset[$clog2(SramDw / 8) +: SramAw]);
   parameter sram_addr_t SramPayloadIdx  = SramIngressIdx;
   parameter sram_addr_t SramPayloadSize = sram_addr_t'(SramPayloadDepth);
+  `ASSERT_STATIC_IN_PACKAGE(CheckPayloadOffset,
+      (SramPayloadIdx - SramIngressIdx) == spi_device_reg_pkg::SramPayloadOffset)
 
   parameter sram_addr_t SramCmdFifoIdx  = SramPayloadIdx + SramPayloadSize;
   parameter sram_addr_t SramCmdFifoSize = sram_addr_t'(SramCmdFifoDepth);
+  `ASSERT_STATIC_IN_PACKAGE(CheckCmdFifoOffset,
+      (SramCmdFifoIdx - SramIngressIdx) == spi_device_reg_pkg::SramCmdFifoOffset)
 
   parameter sram_addr_t SramAddrFifoIdx  = SramCmdFifoIdx + SramCmdFifoSize;
   parameter sram_addr_t SramAddrFifoSize = sram_addr_t'(SramAddrFifoDepth);
+  `ASSERT_STATIC_IN_PACKAGE(CheckAddrFifoOffset,
+      (SramAddrFifoIdx - SramIngressIdx) == spi_device_reg_pkg::SramAddrFifoOffset)
 
   // Max BitCount in a transaction
   parameter int unsigned BitLength = SramMsgDepth * 32;

diff --git a/hw/ip/spi_device/rtl/spi_device_reg_pkg.sv b/hw/ip/spi_device/rtl/spi_device_reg_pkg.sv
@@ -10,6 +10,18 @@ package spi_device_reg_pkg;
   parameter int unsigned SramDepth = 1024;
   parameter int unsigned SramEgressDepth = 832;
   parameter int unsigned SramIngressDepth = 96;
+  parameter int unsigned SramReadBufferOffset = 0;
+  parameter int unsigned SramReadBufferDepth = 512;
+  parameter int unsigned SramMailboxOffset = 512;
+  parameter int unsigned SramMailboxDepth = 256;
+  parameter int unsigned SramSfdpOffset = 768;
+  parameter int unsigned SramSfdpDepth = 64;
+  parameter int unsigned SramPayloadOffset = 0;
+  parameter int unsigned SramPayloadDepth = 64;
+  parameter int unsigned SramCmdFifoOffset = 64;
+  parameter int unsigned SramCmdFifoDepth = 16;
+  parameter int unsigned SramAddrFifoOffset = 80;
+  parameter int unsigned SramAddrFifoDepth = 16;
   parameter int unsigned NumCmdInfo = 24;
   parameter int unsigned NumLocality = 5;
   parameter int unsigned TpmWrFifoPtrW = 7;

diff --git a/sw/device/lib/dif/dif_spi_device.c b/sw/device/lib/dif/dif_spi_device.c
@@ -13,16 +13,25 @@
 #define DIF_SPI_DEVICE_TPM_FIFO_DEPTH 16
 
 enum { kDifSpiDeviceFlashStatusWelBit = 1 };
-enum { kDifSpiDeviceEFlashLen = 2048 };
-enum { kDifSpiDeviceMailboxLen = 1024 };
-enum { kDifSpiDeviceSfdpLen = 256 };
-enum { kDifSpiDevicePayloadLen = 256 };
+enum {
+  kDifSpiDeviceEFlashLen =
+      SPI_DEVICE_PARAM_SRAM_READ_BUFFER_DEPTH * sizeof(uint32_t),
+  kDifSpiDeviceMailboxLen =
+      SPI_DEVICE_PARAM_SRAM_MAILBOX_DEPTH * sizeof(uint32_t),
+  kDifSpiDeviceSfdpLen = SPI_DEVICE_PARAM_SRAM_SFDP_DEPTH * sizeof(uint32_t),
+  kDifSpiDevicePayloadLen =
+      SPI_DEVICE_PARAM_SRAM_PAYLOAD_DEPTH * sizeof(uint32_t),
+};
 
 enum {
-  kDifSpiDeviceEFlashOffset = 0,
-  kDifSpiDeviceMailboxOffset = 2048,
-  kDifSpiDeviceSfdpOffset = 3072,
-  kDifSpiDevicePayloadOffset = 0,
+  kDifSpiDeviceEFlashOffset =
+      SPI_DEVICE_PARAM_SRAM_READ_BUFFER_OFFSET * sizeof(uint32_t),
+  kDifSpiDeviceMailboxOffset =
+      SPI_DEVICE_PARAM_SRAM_MAILBOX_OFFSET * sizeof(uint32_t),
+  kDifSpiDeviceSfdpOffset =
+      SPI_DEVICE_PARAM_SRAM_SFDP_OFFSET * sizeof(uint32_t),
+  kDifSpiDevicePayloadOffset =
+      SPI_DEVICE_PARAM_SRAM_PAYLOAD_OFFSET * sizeof(uint32_t),
 };
 
 /**