[ipgen,rstmgr] Fix englishbreakfast verilator build

Signed-off-by: Guillermo Maturana <[email protected]>
lowRISC · Jan 15, 2024 · f4569a0 · f4569a0
1 parent 20e643e
commit f4569a0
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Showing 7 changed files with 90 additions and 12 deletions.
diff --git a/azure-pipelines.yml b/azure-pipelines.yml
@@ -220,15 +220,21 @@ jobs:
       echo -//quality/... >> "${TARGET_PATTERN_FILE}"
       echo -//sw/otbn/crypto/... >> "${TARGET_PATTERN_FILE}"
       echo -//third_party/riscv-compliance/... >> "${TARGET_PATTERN_FILE}"
-      echo -//hw:all >> "${TARGET_PATTERN_FILE}"
+      # echo -//hw:all >> "${TARGET_PATTERN_FILE}"
+      ./bazelisk.sh cquery "deps(//hw:all)" \
+        --output=starlark \
+        --starlark:expr='"-{}".format(target.label)' \
+        >> "${TARGET_PATTERN_FILE}"
       ./bazelisk.sh cquery \
         --noinclude_aspects \
         --output=starlark \
         --starlark:expr='"-{}".format(target.label)' \
         --define DISABLE_VERILATOR_BUILD=true \
         -- "rdeps(//..., kind(bitstream_splice, //...))" \
         >> "${TARGET_PATTERN_FILE}"
-
+      echo "target pattern file"
+      cat ${TARGET_PATTERN_FILE}
+      echo "build sw targets"
       # Build all unit tests and their dependencies.
       ci/bazelisk.sh build \
         --build_tests_only=false \
@@ -291,8 +297,9 @@ jobs:
 - job: chip_englishbreakfast_verilator
   displayName: Verilated English Breakfast (Build)
   # Build Verilator simulation of the English Breakfast toplevel design
-  dependsOn: lint
-  condition: and(succeeded(), eq(dependencies.lint.outputs['DetermineBuildType.onlyDocChanges'], '0'), eq(dependencies.lint.outputs['DetermineBuildType.onlyCdcChanges'], '0'))
+  dependsOn: checkout
+  # dependsOn: lint
+  # condition: and(succeeded(), eq(dependencies.lint.outputs['DetermineBuildType.onlyDocChanges'], '0'), eq(dependencies.lint.outputs['DetermineBuildType.onlyCdcChanges'], '0'))
   pool:
     vmImage: ubuntu-20.04
   steps:
@@ -304,6 +311,26 @@ jobs:
       verilator --version
       verible-verilog-lint --version
     displayName: Display environment
+  - bash: |
+      ci/scripts/build-chip-setup.sh englishbreakfast
+      tar -C $(Pipeline.Workspace)/opentitan-repo -czf $(Pipeline.Workspace)/opentitan-repo-build.tar.gz .
+    displayName: Setup simulation with Verilator
+  - publish: $(Pipeline.Workspace)/opentitan-repo-build.tar.gz
+    artifact: opentitan-with-build
+    displayName: Upload opentitan-with-build
+  # The repo should have all generated artifacts at this point.
+  - bash: |
+      echo "a" && ls $(Pipeline.Workspace)/a
+      echo "b" && ls $(Pipeline.Workspace)/b
+      echo "s" && ls $(Pipeline.Workspace)/s
+      echo "repo" && ls $(Pipeline.Workspace)/opentitan-repo
+      echo "Verilator version" && fusesoc --version
+  - bash: |
+      tar -C $(Build.StagingDirectory) -czf $(Pipeline.Workspace)/eng_staging_dir.tar.gz .
+    # displayName: Pack up eng_staging_dif
+  - publish: $(Pipeline.Workspace)/eng_staging_dir.tar.gz
+    artifact: eng_staging_dir
+    displayName: Upload eng_staging_dir
   - bash: ci/scripts/build-chip-verilator.sh englishbreakfast
     displayName: Build simulation with Verilator
   - template: ci/upload-artifacts-template.yml

diff --git a/ci/scripts/build-chip-setup.sh b/ci/scripts/build-chip-setup.sh
@@ -0,0 +1,48 @@
+#!/bin/bash
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+# Build a chip-level verilator simulation
+#
+# Expects three arguments: the toplevel to build, the fusesoc core and
+# the intermediate Verilated binary name
+
+set -e
+
+if [ $# != 1 ]; then
+    echo >&2 "Usage: build-chip-verilator.sh <toplevel>"
+    exit 1
+fi
+tl="$1"
+
+case "$tl" in
+    earlgrey)
+        fileset=fileset_top
+        fusesoc_core=lowrisc:dv:chip_verilator_sim
+        ;;
+    englishbreakfast)
+        fileset=fileset_topgen
+        fusesoc_core=lowrisc:systems:chip_englishbreakfast_verilator
+        # Englishbreakfast on CI runs on a 2-core CPU
+        util/topgen-fusesoc.py --files-root=. --topname=top_englishbreakfast
+        ;;
+    *)
+        echo >&2 "Unknown toplevel: $tl"
+        exit 1
+esac
+
+# Move to project root
+cd "$(git rev-parse --show-toplevel)"
+
+. util/build_consts.sh
+
+set -x
+
+mkdir -p "$OBJ_DIR/hw"
+mkdir -p "$BIN_DIR/hw/top_${tl}"
+
+fusesoc --cores-root=. \
+  run --flag=$fileset --target=simple --setup \
+  --build-root="$OBJ_DIR/hw" \
+  $fusesoc_core
diff --git a/hw/top_englishbreakfast/chip_englishbreakfast_verilator.core b/hw/top_englishbreakfast/chip_englishbreakfast_verilator.core
@@ -79,6 +79,12 @@ targets:
       - files_sim_verilator
     toplevel: chip_englishbreakfast_verilator
 
+  simple: &simple_target
+    toplevel: chip_englishbreakfast_verilator
+    filesets:
+      - files_sim_verilator
+    default_tool: vcs
+
   sim:
     parameters:
       - PRIM_DEFAULT_IMPL=prim_pkg::ImplGeneric
@@ -97,6 +103,7 @@ targets:
       verilator:
         mode: cc
         verilator_options:
+          # - '-E'
           # Disabling tracing reduces compile times but doesn't have a
           # huge influence on runtime performance.
           - '--trace'

diff --git a/hw/top_englishbreakfast/data/top_englishbreakfast.hjson b/hw/top_englishbreakfast/data/top_englishbreakfast.hjson
@@ -257,7 +257,7 @@
       param_decl: {
         SecCheck: "0",
       }
-      attr: "templated",
+      attr: "ipgen",
     },
     { name: "clkmgr_aon",
       type: "clkmgr",

diff --git a/hw/top_englishbreakfast/util/prepare_sw.py b/hw/top_englishbreakfast/util/prepare_sw.py
@@ -145,7 +145,7 @@ def main():
         'ip/clkmgr/data/autogen/clkmgr.hjson',
         'ip/flash_ctrl/data/autogen/flash_ctrl.hjson',
         'ip_autogen/pwrmgr/data/pwrmgr.hjson',
-        'ip/rstmgr/data/autogen/rstmgr.hjson',
+        'ip_autogen/rstmgr/data/rstmgr.hjson',
         'ip/pinmux/data/autogen/pinmux.hjson',
         'ip_autogen/rv_plic/data/rv_plic.hjson',
         'ip/ast/data/ast.hjson',

diff --git a/topgen-reg-only.core b/topgen-reg-only.core
@@ -11,7 +11,6 @@ filesets:
       - lowrisc:ip:clkmgr_reggen
       - lowrisc:ip:flash_ctrl_reggen
       - lowrisc:ip:pinmux_reggen
-      - lowrisc:ip:rstmgr_reggen
 
 targets:
   default: &default

diff --git a/util/topgen-fusesoc.py b/util/topgen-fusesoc.py
@@ -75,11 +75,10 @@ def main():
         'clkmgr': '',
         'flash_ctrl': '_core',
         'pinmux': '',
-        'rstmgr': '',
     }
 
     # reg-only
-    for ip in ['clkmgr', 'flash_ctrl', 'pinmux', 'rstmgr']:
+    for ip in ['clkmgr', 'flash_ctrl', 'pinmux']:
         core_filepath = os.path.abspath(os.path.join(files_out, 'generated-%s.core' % ip))
         name = 'lowrisc:ip:%s_reggen' % ip,
         files = ['ip/%s/rtl/autogen/%s_reg_pkg.sv' % (ip, ip),
@@ -126,7 +125,7 @@ def main():
                     'lowrisc:prim:util',
                     'lowrisc:ip:lc_ctrl_pkg',
                     'lowrisc:ip:pwrmgr_pkg',
-                    # rstmgr
+                    'lowrisc:ip:rstmgr_pkg',
                     'lowrisc:prim:clock_mux2',
                     # clkmgr
                     'lowrisc:prim:all',
@@ -147,8 +146,6 @@ def main():
                     'ip/flash_ctrl/rtl/autogen/flash_ctrl_pkg.sv',
                     'ip/flash_ctrl/rtl/autogen/flash_ctrl.sv',
                     'ip/flash_ctrl/rtl/autogen/flash_ctrl_region_cfg.sv',
-                    'ip/rstmgr/rtl/autogen/rstmgr_pkg.sv',
-                    'ip/rstmgr/rtl/autogen/rstmgr.sv',
                     # Top
                     'rtl/autogen/%s_rnd_cnst_pkg.sv' % topname,
                     'rtl/autogen/%s_pkg.sv' % topname,