[pwm,dv] Enable stress_all_with_rand_reset test

Signed-off-by: Rupert Swarbrick <[email protected]>

hw/ip/pwm/dv/env/pwm_env_cfg.sv

@@ -6,8 +6,6 @@ class pwm_env_cfg extends cip_base_env_cfg #(.RAL_T(pwm_reg_block));
   `uvm_object_utils_begin(pwm_env_cfg)
   `uvm_object_utils_end
 
-  `uvm_object_new
-
   // configs
   pwm_monitor_cfg       m_pwm_monitor_cfg[PWM_NUM_CHANNELS];
 
@@ -20,13 +18,20 @@ class pwm_env_cfg extends cip_base_env_cfg #(.RAL_T(pwm_reg_block));
   rand int unsigned clk_scale;
   constraint clk_scale_c { clk_scale inside {[256:1024]}; }
 
+  extern function new (string name="");
+
   // Method from dv_base_env_cfg. Construct RAL models and fill in monitor configs.
   extern virtual function void initialize(bit [31:0] csr_base_addr = '1);
 
   // Return the scaled frequency in MHz for the core
   extern virtual function int get_clk_core_freq();
 endclass : pwm_env_cfg
 
+function pwm_env_cfg::new (string name="");
+  super.new(name);
+  can_reset_with_csr_accesses = 1'b1;
+endfunction
+
 function void pwm_env_cfg::initialize(bit [31:0] csr_base_addr = '1);
   list_of_alerts = pwm_env_pkg::LIST_OF_ALERTS;
   super.initialize(csr_base_addr);

hw/ip/pwm/dv/pwm_sim_cfg.hjson

@@ -30,7 +30,7 @@
                 "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson",
                 "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson",
                 "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson",
-                //"{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson",
+                "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson",
                 "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson",
                 "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson"]
 
@@ -83,11 +83,6 @@
       name: pwm_perf
       uvm_test_seq: pwm_perf_vseq
     }
-    {
-      name: pwm_stress_all
-      uvm_test_seq: pwm_stress_all_vseq
-      run_opts:["+test_timeout_ns=10_000_000_000"]
-    }
   ]
 
   // List of regressions.